ADV7611 RGB888 640*480 Output the VsyncTiming Controls Register Setting Question

Hi,

 The HS_START and HS_END will move Hsync edges .Similarly VS_START and VS_END will move Vsync edges. The user can reposition the synchronization signal output from the regenerated input synchronization signal within the CP block with the control bits start_hs[9:0] / end_hs[9:0]  /start_vs[3:0] / end_vs[3:0] / start_fe[3:0] / start_fo[3:0] .

 Please note that, Start_vs and End_vs only move the edges by +/- 8 lines but generally we do not have to do this either since the source will generate the correct VS and HS signals.

 For example, "The picture gets shifted by a number of clocks equal to the hsync width. For example, the hsync width is 40 clock cycles for 720p, so the picture would get shifted by 40 pixel clocks".

  Note: START_HS and END_HS adjust the HS timing based on the input HSYNC pulse.  So if START_HS = 0 then HS start should be the same as incoming hsync.  The same applies for the END_HS.  The Active video pixels are based on the incoming sync pulses and these register just move the output sync edges.  There is no direct relationship between active video pixels and trailing hsync pulse, just indirect based on the incoming pulse.

 DE = Hysnc anded with Vsync, assuming hsync and vsync are expanded to cover the entire blanking area.

 From this below table for 480P, you can take the Vs default configuration values from 525i/625i

Thanks,

Poornima

Hi,

 The HS_START and HS_END will move Hsync edges .Similarly VS_START and VS_END will move Vsync edges. The user can reposition the synchronization signal output from the regenerated input synchronization signal within the CP block with the control bits start_hs[9:0] / end_hs[9:0]  /start_vs[3:0] / end_vs[3:0] / start_fe[3:0] / start_fo[3:0] .

 Please note that, Start_vs and End_vs only move the edges by +/- 8 lines but generally we do not have to do this either since the source will generate the correct VS and HS signals.

 For example, "The picture gets shifted by a number of clocks equal to the hsync width. For example, the hsync width is 40 clock cycles for 720p, so the picture would get shifted by 40 pixel clocks".

  Note: START_HS and END_HS adjust the HS timing based on the input HSYNC pulse.  So if START_HS = 0 then HS start should be the same as incoming hsync.  The same applies for the END_HS.  The Active video pixels are based on the incoming sync pulses and these register just move the output sync edges.  There is no direct relationship between active video pixels and trailing hsync pulse, just indirect based on the incoming pulse.

 DE = Hysnc anded with Vsync, assuming hsync and vsync are expanded to cover the entire blanking area.

 From this below table for 480P, you can take the Vs default configuration values from 525i/625i

Thanks,

Poornima