ADV7842 detects TMDS clock and that it's locked, but measured frequency is always 0.

Hi,

  In order to accurately measure the Primary port, the background measurement needs to be set the same as port as the primary port. So the background control allows you to check everyport but you need to set in back to the primary port when reading measurements from the primary port So please read the background registers and let us know about that.

 In order to read the below background registers, We have to set "BG_MEAS_REQ" (By setting this control sends a request to update the synchronization parameter measurements of the currently selected background port and  "BG_MEAS_PORT_SEL[1:0]" ( It selects a background port on which HDMI measurements are to be made and provided in the background measurement registers).

Thanks,

Poornima

Thanks for the reply. I get all 0's for the background measurement as well. Any other ideas?

Hi,

  We will check such registers in our eval board and let you know about that.

   Also Please let us know, Is there any issue on the Video output ?

   Meanwhile please check Are you seeing any signal on the VS, HS and DE pins?

    Note that the synchronization parameters are valid if the part is configured in HDMI mode via PRIM_MODE[3:0]. 

Thanks,

Poornima

Poornima,

The output of the ADV7842 is connected to an FPGA that has a logic analyzer in it. When in VGA mode or Free Run mode I see expected data. When in HDMI mode, I see a clock, VSync, HSync and DE, but the timing of HSync and DE does not look correct. They are interleaved instead of DE being inside of HSync.

The clock does change when the input resolution changes and seems to be correct.

Hi,

  If Possible, Could you please share your register configuration.

  Please ensure with Power supply and it is the most likely be an problem with PLL (PVDD) power supply might be an noisy .

  The exposed pad on the chip is soldered to ground.

  Also ensure with source, For example If the source is inputting a strange Vsync timings then this timing and that will be reflected through the entire path. (Hsync and Vsync are encoded in the same symbol in the input video stream. Therefore they should be whatever the source is outputting).

Thanks,

Poornima

Poornima,

I have tried many configurations, A log showing the writes/reads is below.

The power supplies have a little noise, but I'm not sure if it is too much.

The part is a BGA so it does not have an exposed pad.

The source is an Extron VTG400 that displays fine on a monitor.

Starting ADV7842 Input Test App
I2C Interface initialized
ADV7842HWReset
I2C Mux selected
ADV7842 Read: Addr: 0x20 Register: 0xEA Data: 0x20
ADV7842 Read: Addr: 0x20 Register: 0xEB Data: 0x12
ADV7842 ID Read: 0x2012
ADV7842Init
ADV7842 Write: Addr: 0x20 Register: 0xF1 Data: 0x92
ADV7842 Write: Addr: 0x20 Register: 0xF2 Data: 0x94
ADV7842 Write: Addr: 0x20 Register: 0xF3 Data: 0x84
ADV7842 Write: Addr: 0x20 Register: 0xF4 Data: 0x80
ADV7842 Write: Addr: 0x20 Register: 0xF5 Data: 0x82
ADV7842 Write: Addr: 0x20 Register: 0xF8 Data: 0x4C
ADV7842 Write: Addr: 0x20 Register: 0xF9 Data: 0x64
ADV7842 Write: Addr: 0x20 Register: 0xFA Data: 0x6C
ADV7842 Write: Addr: 0x20 Register: 0xFB Data: 0x68
ADV7842 Write: Addr: 0x20 Register: 0xFD Data: 0x44
ADV7842 Write: Addr: 0x20 Register: 0xFE Data: 0x48
ADV7842 Write: Addr: 0x20 Register: 0x00 Data: 0x0C
ADV7842 Write: Addr: 0x20 Register: 0x01 Data: 0x02
ADV7842 Write: Addr: 0x20 Register: 0x02 Data: 0xF2
ADV7842 Write: Addr: 0x20 Register: 0x03 Data: 0x40
ADV7842 Write: Addr: 0x20 Register: 0x05 Data: 0x28
ADV7842 Write: Addr: 0x20 Register: 0x06 Data: 0xA6
ADV7842 Write: Addr: 0x20 Register: 0x40 Data: 0xC2
ADV7842 Write: Addr: 0x20 Register: 0x0C Data: 0x42
ADV7842 Write: Addr: 0x20 Register: 0x33 Data: 0x00
ADV7842 Write: Addr: 0x20 Register: 0x44 Data: 0x90
ADV7842 Write: Addr: 0x20 Register: 0x15 Data: 0xB0
ADV7842 Write: Addr: 0x22 Register: 0x3E Data: 0x00
ADV7842 Write: Addr: 0x22 Register: 0x73 Data: 0xEA
ADV7842 Write: Addr: 0x22 Register: 0x74 Data: 0x8A
ADV7842 Write: Addr: 0x22 Register: 0x75 Data: 0xA2
ADV7842 Write: Addr: 0x22 Register: 0x76 Data: 0xA8
ADV7842 Write: Addr: 0x22 Register: 0x85 Data: 0x03
ADV7842 Write: Addr: 0x22 Register: 0x91 Data: 0x00
ADV7842 Write: Addr: 0x22 Register: 0xC3 Data: 0x39
ADV7842 Write: Addr: 0x26 Register: 0x0C Data: 0x1F
ADV7842 Write: Addr: 0x26 Register: 0x12 Data: 0x63
ADV7842 Write: Addr: 0x26 Register: 0x00 Data: 0x88
ADV7842 Write: Addr: 0x26 Register: 0x02 Data: 0x00
ADV7842 Write: Addr: 0x26 Register: 0xC8 Data: 0x33
ADV7842 Write: Addr: 0x34 Register: 0x00 Data: 0x02
ADV7842 Write: Addr: 0x34 Register: 0x01 Data: 0x40
ADV7842 Write: Addr: 0x34 Register: 0x01 Data: 0x80
ADV7842 Write: Addr: 0x34 Register: 0x1A Data: 0x1A
ADV7842 Write: Addr: 0x34 Register: 0x9D Data: 0x02
ADV7842 Write: Addr: 0x4A Register: 0x29 Data: 0x10
ADV7842 Write: Addr: 0x4A Register: 0x12 Data: 0x00
ADV7842 Write: Addr: 0x4A Register: 0x39 Data: 0x40
ADV7842 Write: Addr: 0x4A Register: 0x0E Data: 0x10
ADV7842 Write: Addr: 0x20 Register: 0x6E Data: 0x22
ADV7842 Write: Addr: 0x20 Register: 0x87 Data: 0x02

-----------------------------------------------------
-- Menu --
-----------------------------------------------------

f = Free Run Mode
d = DVI Mode (1280 x 1024)
v = VGA Mode (1024 x 768 @ 60)
r = Reset ADV7842
i = Initialize ADV7842
m = Fire ADV7842 Interrupt

-----------------------------------------------------
UserInput: d
ADV7842 Write: Addr: 0x20 Register: 0x00 Data: 0x05
ADV7842 Write: Addr: 0x34 Register: 0x00 Data: 0x2A
ADV7842 Write: Addr: 0x20 Register: 0x01 Data: 0x06
ADV7842 Write: Addr: 0x20 Register: 0x02 Data: 0x12
ADV7842 Write: Addr: 0x20 Register: 0x03 Data: 0x40
ADV7842 Write: Addr: 0x20 Register: 0x05 Data: 0x28
ADV7842 Write: Addr: 0x34 Register: 0xC1 Data: 0xFF
ADV7842 Write: Addr: 0x34 Register: 0xC2 Data: 0xFF
ADV7842 Write: Addr: 0x34 Register: 0xC3 Data: 0xFF
ADV7842 Write: Addr: 0x34 Register: 0xC4 Data: 0xFF
ADV7842 Write: Addr: 0x34 Register: 0xC5 Data: 0x00
ADV7842 Write: Addr: 0x34 Register: 0xC6 Data: 0x00
ADV7842 Write: Addr: 0x34 Register: 0xC0 Data: 0xFF
ADV7842 Write: Addr: 0x20 Register: 0x0C Data: 0x42
ADV7842 Write: Addr: 0x20 Register: 0x14 Data: 0x3F
ADV7842 Write: Addr: 0x20 Register: 0x15 Data: 0x80
ADV7842 Write: Addr: 0x20 Register: 0x33 Data: 0x00
ADV7842 Write: Addr: 0x34 Register: 0xC0 Data: 0x00
ADV7842 Write: Addr: 0x34 Register: 0x0D Data: 0x34
ADV7842 Write: Addr: 0x34 Register: 0x3D Data: 0x10
ADV7842 Write: Addr: 0x34 Register: 0x44 Data: 0x85
ADV7842 Write: Addr: 0x34 Register: 0x46 Data: 0x1F
ADV7842 Write: Addr: 0x34 Register: 0x57 Data: 0xB6
ADV7842 Write: Addr: 0x34 Register: 0x58 Data: 0x03
ADV7842 Write: Addr: 0x34 Register: 0x60 Data: 0x88
ADV7842 Write: Addr: 0x34 Register: 0x61 Data: 0x88
ADV7842 Write: Addr: 0x34 Register: 0x6C Data: 0x18
ADV7842 Write: Addr: 0x34 Register: 0x75 Data: 0x10
ADV7842 Write: Addr: 0x34 Register: 0x85 Data: 0x1F
ADV7842 Write: Addr: 0x34 Register: 0x87 Data: 0x70
ADV7842 Write: Addr: 0x34 Register: 0x89 Data: 0x04
ADV7842 Write: Addr: 0x34 Register: 0x99 Data: 0xA1
ADV7842 Write: Addr: 0x34 Register: 0x9B Data: 0x09
ADV7842 Write: Addr: 0x26 Register: 0x00 Data: 0xFF
ADV7842 Write: Addr: 0x26 Register: 0x01 Data: 0xFE
ADV7842 Write: Addr: 0x22 Register: 0x3E Data: 0x00
ADV7842 Write: Addr: 0x34 Register: 0x8A Data: 0x1E
ADV7842 Write: Addr: 0x34 Register: 0x93 Data: 0x04
ADV7842 Write: Addr: 0x34 Register: 0x94 Data: 0x1E
ADV7842 Write: Addr: 0x34 Register: 0x9D Data: 0x02
ADV7842 Write: Addr: 0x34 Register: 0x9D Data: 0x02
ADV7842 Write: Addr: 0x34 Register: 0x5A Data: 0x20
ADV7842 Read: Addr: 0x22 Register: 0x8B Data: 0x40
ADV7842 Write: Addr: 0x22 Register: 0x8B Data: 0x40
ADV7842 Write: Addr: 0x22 Register: 0x8C Data: 0x00
ADV7842 Read: Addr: 0x22 Register: 0x8B Data: 0x40
ADV7842 Write: Addr: 0x22 Register: 0x8B Data: 0x40
ADV7842 Write: Addr: 0x22 Register: 0x8D Data: 0x00
ADV7842 Write: Addr: 0x22 Register: 0x8E Data: 0x00
ADV7842 Read: Addr: 0x34 Register: 0x05 Data: 0x00
HDMI Mode (1) or DVI Mode (0): 0x00
ADV7842 Read: Addr: 0x34 Register: 0xEB Data: 0x00
BG HDMI Mode (1) or DVI Mode (0): 0x00
ADV7842 Read: Addr: 0x20 Register: 0x6A Data: 0x22
TMDS Clk Det: 0x02
ADV7842 Read: Addr: 0x20 Register: 0x6A Data: 0x22
TMDS Lock:0x20
ADV7842 Read: Addr: 0x34 Register: 0x04 Data: 0x22
TMDS Lock (HDMI):0x02
ADV7842 Read: Addr: 0x34 Register: 0xEA Data: 0x00
BG Param Lock:0x00
ADV7842 Read: Addr: 0x34 Register: 0xE0 Data: 0x00
ADV7842 Read: Addr: 0x34 Register: 0xE1 Data: 0x00
BG Clock Freq:0x0
ADV7842 Read: Addr: 0x34 Register: 0x51 Data: 0x00
ADV7842 Read: Addr: 0x34 Register: 0x52 Data: 0x00
Clock Freq:0x0

Hi,

  Here in our eval board, We don't face any issue while reading "TMDSFREQ" register. 

  Please note that, TMDS PLL must be locked to the incoming TMDS clock in order for the "TMDSFREQ and TMDSFREQ_FRAC" registers to return a Valid measurement.

  Also let us know, whether are you using any DVI type of source? but it should work with DVI source also.

  At first, Please check with standard formats like "1080p/720p/480p" in HDMI mode instead of checking with "1280x1024" format and let us know.

Thanks,

Poornima

Hi Jeff,

      If it is an HDMI Supported Part, Please go through the below mentioned FAQs before using an Part and these FAQs can contains many useful information.

      If Possible, Please go through these links. It will be more helpful.

Thanks,

Poornima

Poornima,

I got pulled away from this but am now getting back to it.

A few questions:

1) What is the easiest way to ensure the 28.63MHz crystal is connected and functioning? Does the I2C commination use this?

2) Does the RXA_5V signal come into play when trying to measure the TMDS clock frequency?

Thanks,

Jeff

This problem is solved. For reasons I can't explain, I grounded RXA_5V, which apparently holds the HDMI circuit in reset. There is a way to disable this by writing to HDMI register 0x48.

Thanks for the help!