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ADV7842 - how to shift picture a few pixels down

Category: Hardware
Product Number: ADV7842

Hello,

I'm capturing the video from the LD player and the picture is a little bit shifted to the top and to the right that results in cutting a few pixels on the top and right edges. I would like to shift it down and to the left. What is the registry command to do that? Thanks.

PS. This issue is the same as thisRE: ADV7842 SDP Shift 



Added a link to the related issue.
[edited by: metaleonid at 1:57 AM (GMT -4) on 3 Apr 2023]
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  • Hi,

    Could you please try with reference script which is available at ADV7842 Design Support Files - Documents - Video - EngineerZone (analog.com) & from the default reference configuration you may not get such pixel shift .

    Also try with some other sources instead of LD player.

    The position of the signal can be controlled be using below register and kindly configure these registers accordingly, For more details, Please refer section "OUTPUT SYNCHRONIZATION SIGNAL POSITIONING" at UG-214: ADV7842 Hardware User Guide

     How should we set START_VS and END_VS ?

         The picture gets shifted by a number of clocks equal to the hsync width. For example, the hsync width is 40 clock cycles for 720p, so the picture would get shifted by 40 pixel clocks.

         If you look at the CEA-861 specification, you will see that the 640x480p @ 59.94/60Hz has an hsync width of 96 clock cycles.

    The DE sync leading and trailing edges must therefore be shifted by 96 pixels towards the left, i.e.:

    • de_h_start[9:0] = 0x3A0 (-96 pixels of shift)

    • de_h_end[9:0] = 0x3A0 (-96 pixels of shift)

    This results in the following settings (the sequence of the writes is important and must be followed):

    44 8B 43; de_h_end shifted by -96 pixels

    44 8C A0; de_h_end shifted by -96 pixels

    44 8B 4F; de_h_start shifted by -96 pixels

    44 8D A0; de_h_start shifted by -96 pixels

    Thanks,

    Poornima

Reply
  • Hi,

    Could you please try with reference script which is available at ADV7842 Design Support Files - Documents - Video - EngineerZone (analog.com) & from the default reference configuration you may not get such pixel shift .

    Also try with some other sources instead of LD player.

    The position of the signal can be controlled be using below register and kindly configure these registers accordingly, For more details, Please refer section "OUTPUT SYNCHRONIZATION SIGNAL POSITIONING" at UG-214: ADV7842 Hardware User Guide

     How should we set START_VS and END_VS ?

         The picture gets shifted by a number of clocks equal to the hsync width. For example, the hsync width is 40 clock cycles for 720p, so the picture would get shifted by 40 pixel clocks.

         If you look at the CEA-861 specification, you will see that the 640x480p @ 59.94/60Hz has an hsync width of 96 clock cycles.

    The DE sync leading and trailing edges must therefore be shifted by 96 pixels towards the left, i.e.:

    • de_h_start[9:0] = 0x3A0 (-96 pixels of shift)

    • de_h_end[9:0] = 0x3A0 (-96 pixels of shift)

    This results in the following settings (the sequence of the writes is important and must be followed):

    44 8B 43; de_h_end shifted by -96 pixels

    44 8C A0; de_h_end shifted by -96 pixels

    44 8B 4F; de_h_start shifted by -96 pixels

    44 8D A0; de_h_start shifted by -96 pixels

    Thanks,

    Poornima

Children
  • Thank you very much. I will try tomorrow and will let you know. 

  • Hi Poornima,

    Unfortunately, this series didn't do anything. I expected to shift the image, but it did't. I'd like to ask you how you arrived to the numbers. x3A0 is 1110100000 in binary which is 928 in decimal. What is the connection between 928 and -96? I'd like to play with it and try different numbers. 

    I'm attaching the screenshot of the video capture. Take a look how image is shifted to the right and to the top. All I need to do is to shift it back. Thank you.

  • Hi,

       Our chip will not introduce any shift with default settings so could you please configure according to same as like our reference script at 7725.ADV7842_Evaluation_Board_Documents.zip and let us know the result with default configuration.

      Also Please refer this thread and here expert given some suggestion about video image twisting at Video image twisting with ADV7619 to receive 4K HDMI video stream - Q&A - Video - EngineerZone (analog.com)

    Thanks,

    Poornima

  • Hi Poornima,

    I tried the script that you provided with the default settings but it didn't fix the issue at all. In fact the image is even further shifted to the right. Here're the screenshots. Can you please provide the solution / workaround how to shift the image back (in this case to the left and down). Thank you.

    PS. The S-Video image is horrible (the second one). For some reason the board produces the "net" artifacts. I don't have to use S-Video but just letting you know.

  • Hi Poornima,

    I just tried the capturing from the DVD player 1st outputting directly HDMI into my capture device. And in the 2nd capture I was using composite-in into ADV7842 board and then HDMI out to my capture device. As you see the image from the direct capture - it is not shifted. But using ADV7842 it is shifted to the top-right. I would like to play with the register settings for horizontal and vertical shift. But can you confirm if I correctly got it at the bottom of this message?

    Directly from DVD - not shifted.

    Composite into ADV7842 - shifted to the top-right

    Regarding the shift. If I want to shift 96 pixels to the left, I need to subtract 96 from 1024, right?

    1024 - 96 = 928 = 0x3A0

    44 8B 43; de_h_end shifted by -96 pixels

    44 8C A0; de_h_end shifted by -96 pixels

    Is this how it is computed?

    0x3A0 = 11 1010 0000

    0xA0 shall go to both 44 8C (d_h_end) and 44 8D (d_h_start)

    And the number 0x3 = 11 shall go to register 44 8B. 

    My understanding is that register 44 8B has two right-most bits for de_h_end [1:0] and bits 3rd and 4th are for d_h_start [3:2].

    Thus putting 0x3 in in [1:0] and then in [3:2] is same as putting 0xF into 44 4B [3:0]

    Is this right?

    Anyhow, the writing to these registers does not shift the image. Is there anything else? The progressive footage does not suffer from this problem. The image is not shifted. Only interlaced. But my sources are interlaced.

  • Hi  

    My issue is the same as this one:

     RE: ADV7842 SDP Shift 

    Can you please provide the script snippets to adjust values for these registers: DE_V_BEG_O_ADJ, DE_V_BEG_E_ADJ, and DE_H_BEG_ADJ ?

    Thank you.

  • Hi,

      No script is available for adjusting these register values.

      We keep these sync related registers in default values (Default values generally introduce zero shift) So we don't use this registers in our script .

       Also Please refer this thread and here expert gave some suggestions about picture shifting (+) The issue about capturing CVBS/S-Video of ADV7850 - Q&A - Video - EngineerZone (analog.com)

    Thanks,

    Poornima

  •  Hi  ,

    Sorry I was asking for the script snippets (i.e. examples), something like this:

     94 98 00 ; H-DE
       94 99 06 ; 
       94 9A 00 ; 
       94 9B 06 ;

    Can you explain what values I should provide. I am newbie here and I need to understand what this means:

    "The position of the horizontal DE trailing edge is controlled by placing a twos complement number into the SDP_DE_H_END_ADJ[11:0] bits. The number is a twos complement value that allows both positive and negative edge movement. " 

    Can you provide a specific example for the above meaning?

    Can you also advise how to introduce negative shift? Is the sign defined by the leftmost digit? I.e. to shift one pixel to the right, it should be 0x1. To shift one pixel to the left, it should be 0x801?

    The default values do introduce shift if for CVBS/S-Video if the video is 480i - it is evident from the other posts as well.

    Thank you.

    PS. Update.

    I'm able to shift the picture horizontally by using the following command:

     94 98 00 ; H-DE
       94 99 10 ; 
       94 9A 00 ; 
       94 9B 10 ;

    There are 2 horizontal registers: SDP_DE_H_BEG_ADJ and SDP_DE_V_END_E_ADJ. But there are 4 vertical ones.

      can you please explain the difference between:

     SDP_DE_V_BEG_O_ADJ. SDP_DE_V_BEG_E_ADJ, SDP_DE_V_BEG_E_ADJ, SDP_DE_V_BEG_O_ADJ

    What's the difference between E and O?

    Thank you.

  • Hi,

    Please find the below comment,

      The default values do introduce shift if for CVBS/S-Video if the video is 480i - It is evident from the other posts as well ?

           This comment we referred it from Expert at hs adjust and VBI adjust problem - Q&A - Video - EngineerZone (analog.com) .

           Also kindly note that, Sources maybe changing the pulse timing a bit & It depends on the source side (For example One source the video may shifted upwards and for other it shift to right or left) So we have to change the ADV7842 timings based on pixel shifting. If those timing registers are don't change then the Sink will get what the Source sends. 

           And ADV7842 does not modify the timing.  We have to change the sync widths and edge polarity on our own but the default scripts don't do this.

         In that evident post that you have shared, Expert Dave also mentioned like " I duplicated your test on 2 different monitors.  On the first monitor, 1-1e leads to a widescreened image from bezel to bezel and 1-1f leads to a 4:3 image located in the middle of the screen.  On the second monitor, both 1-1e and 1-1f lead to identically positioned and size images-- with no pixel offset of any kind between them ". Please refer the same in respective thread.

    Thanks,

    Poornima

  • Hi  ,

    1. Modifying START_HS, END_HS, START_VS etc registers have absolutely no impact on the problem I described.

    2. I used 2 different LaserDisc players (LD_S2 and CLD-D703) and one DVD player as sources. All of them result in significant top right shift when using CVBS and SVideo 480i default scripts. I provided the screenshots of the problem. While different sources indeed result in different shifts, these shifts are marginal compared to the shift that ADV7842 board introduces. I was not using monitors. I was using HDMI video capture card with VirtualDub application. The HDMI capture card does not introduce the shift (I provided the screenshot of the direct HDMI capture from the DVD player and there was no shift).

    3. The same exact problem was described in this thread 12 years ago:  RE: ADV7842 SDP Shift 

    4. I understand that default script don't modify the needed registers to correct the shift. That is perfectly fine. I wasn't asking to justify that. I was merely asking if it's possible to provide a practical solution to the particular problem I was facing. I.e. how to modify the registers to correct the shift so that I could use it in my custom script. None was provided to me. I figured it out on my own from this old thread.  RE: ADV7842 SDP Shift . Also I don't understand why none of the subsequent questions regarding the various register values were answered.