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ADV7181D PLL Jitter Improvement

Category: Hardware
Product Number: ADV7181D

Regarding EVAL_ADV7181DEBZ, the recommended setting (SD CVBS) of Materials (ADV7181D_ADV7181D@_ADV7341-VER.1.0c.txt) is sent and the CVBS from TSG-170D is input to get Y output.
I checked the SD/HS/3G/12G-SDI performance using this Y output (black burst signal) as a GENLOCK reference, but the SDI timing jitter exceeds the SMPTE standard values.
(PHABRIX's Qx (rasterizer) can measure it) This problem does not occur when the TSG-170D signal is used and directly input as a GENLOCK reference.

Therefore, I think I should improve the PLL clock jitter of the ADV7181D.
I wonder if there is a register to change various PLL settings in SD mode for the better jitter?
As for the resister "0x3C[2:0]: PLL_QPUMP", I tried changing it, but it didn't work very much.

  • Both the ADV7182 and ADV7181D implement Adaptive Digital Line Length Tracking (ADLLT) which is designed to track variable sources like VCRs.  It might be that this circuit adds some jitter noise to the output.  I have no evidence of this.

    One possible test (remove input) is to set the chip in free run mode and check the output jitter again.  Not sure if will give us useful information but i would try if I had the setup here.

  • Regarding EVAL-ADV7181DEBZ, I did Jitter measurement in Free-run (Blue screen).
    Compared to CVBS input, Jitter characteristics changed, but "CVBS-jitter periodic rampage" can be confirmed.
    SDI characteristics (Timing Jitter) when free-run mode output is genlock-synchronized periodically repeats OK and NG of SMPTE standard values. There may be a correlation with "periodic rampage of CVBS-jitter".

    Paste the video.
    001: TG700 Jitter
    002: Jitter when CVBS is input to EVAL-ADV7181D
    003: Jitter in Free-rum mode of EVAL-ADV7181D