Regarding EVAL_ADV7181DEBZ, the recommended setting (SD CVBS) of Materials (ADV7181D_ADV7181D@_ADV7341-VER.1.0c.txt) is sent and the CVBS from TSG-170D is input to get Y output.
I checked the SD/HS/3G/12G-SDI performance using this Y output (black burst signal) as a GENLOCK reference, but the SDI timing jitter exceeds the SMPTE standard values.
(PHABRIX's Qx (rasterizer) can measure it) This problem does not occur when the TSG-170D signal is used and directly input as a GENLOCK reference.
Therefore, I think I should improve the PLL clock jitter of the ADV7181D.
I wonder if there is a register to change various PLL settings in SD mode for the better jitter?
As for the resister "0x3C[2:0]: PLL_QPUMP", I tried changing it, but it didn't work very much.