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ADV7181D PLL Jitter Improvement

Category: Hardware
Product Number: ADV7181D

Regarding EVAL_ADV7181DEBZ, the recommended setting (SD CVBS) of Materials (ADV7181D_ADV7181D@_ADV7341-VER.1.0c.txt) is sent and the CVBS from TSG-170D is input to get Y output.
I checked the SD/HS/3G/12G-SDI performance using this Y output (black burst signal) as a GENLOCK reference, but the SDI timing jitter exceeds the SMPTE standard values.
(PHABRIX's Qx (rasterizer) can measure it) This problem does not occur when the TSG-170D signal is used and directly input as a GENLOCK reference.

Therefore, I think I should improve the PLL clock jitter of the ADV7181D.
I wonder if there is a register to change various PLL settings in SD mode for the better jitter?
As for the resister "0x3C[2:0]: PLL_QPUMP", I tried changing it, but it didn't work very much.

Parents
  • Hi,

      Could you please let us know your Connection Setup ?

      Generally, PLL_DIV_RATIO and VCO_RANGE(i.e TLLC) parameters are automatically set up from the VID_STD settings. For all standards supported by PRIM_MODE and VID_STD, the appropriate VCO range is selected automatically.
      Depending on the required pixel clock frequency, the PLL Divisor Ratio, VCO Range and PLL_QPUMP settings must be set to configure the PLL to generate a stable LLC. Refer to Section 7.3.1(CP PLL Control ) to set the correct PLL Divisor Ratio. The recommended VCO Range and PLL charge pump settings can be set by referring to Table 11 and Equation 3 (Charge Pump Current Calculation ) at 0334.ADV7181D_Manuals.zip

    Thanks,

    Poornima

  • Thank you for your reply.
    I show you the drawing of Connection Setup.

    If there are some registers that improve the SDI characteristics, it would be helpful if you could teach them.
    Thank you for your support.

  • Hi,

      Please let us know your Encoder(DAC) part.

      Also could you please confirm these timing from EVAL ADV7181D output before giving this into PHABRIX QX.

    Thanks,

    Poornima

  • FormerMember
    0 FormerMember
in reply to PoornimaSubramani

PLL jitter can also be caused by schematic implementation and layout

  • Encoder is ADV7341 mounted on EVAL_ADV7181D board.
    The setting is also sending "SD CVBS (Address 0x56)" of "ADV7181D_ADV7181D@_ADV7341-VER.1.0c.txt".
    The Jitter characteristics of Y(DAC1) measured by VM700T are shown below.
    Jitter measurements are very unstable.

    Best regards,

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