ADV7181D PLL Jitter Improvement

Hi,

  Could you please let us know your Connection Setup ?

  Generally, PLL_DIV_RATIO and VCO_RANGE(i.e TLLC) parameters are automatically set up from the VID_STD settings. For all standards supported by PRIM_MODE and VID_STD, the appropriate VCO range is selected automatically.
  Depending on the required pixel clock frequency, the PLL Divisor Ratio, VCO Range and PLL_QPUMP settings must be set to configure the PLL to generate a stable LLC. Refer to Section 7.3.1(CP PLL Control ) to set the correct PLL Divisor Ratio. The recommended VCO Range and PLL charge pump settings can be set by referring to Table 11 and Equation 3 (Charge Pump Current Calculation ) at 0334.ADV7181D_Manuals.zip

Thanks,

Poornima

Thank you for your reply.
I show you the drawing of Connection Setup.

If there are some registers that improve the SDI characteristics, it would be helpful if you could teach them.
Thank you for your support.

Hi,

  Please let us know your Encoder(DAC) part.

  Also could you please confirm these timing from EVAL ADV7181D output before giving this into PHABRIX QX.

Thanks,

Poornima