ADV7181D PLL Jitter Improvement

Hi,

  Could you please let us know your Connection Setup ?

  Generally, PLL_DIV_RATIO and VCO_RANGE(i.e TLLC) parameters are automatically set up from the VID_STD settings. For all standards supported by PRIM_MODE and VID_STD, the appropriate VCO range is selected automatically.
  Depending on the required pixel clock frequency, the PLL Divisor Ratio, VCO Range and PLL_QPUMP settings must be set to configure the PLL to generate a stable LLC. Refer to Section 7.3.1(CP PLL Control ) to set the correct PLL Divisor Ratio. The recommended VCO Range and PLL charge pump settings can be set by referring to Table 11 and Equation 3 (Charge Pump Current Calculation ) at 0334.ADV7181D_Manuals.zip

Thanks,

Poornima

Hi,

  Could you please let us know your Connection Setup ?

  Generally, PLL_DIV_RATIO and VCO_RANGE(i.e TLLC) parameters are automatically set up from the VID_STD settings. For all standards supported by PRIM_MODE and VID_STD, the appropriate VCO range is selected automatically.
  Depending on the required pixel clock frequency, the PLL Divisor Ratio, VCO Range and PLL_QPUMP settings must be set to configure the PLL to generate a stable LLC. Refer to Section 7.3.1(CP PLL Control ) to set the correct PLL Divisor Ratio. The recommended VCO Range and PLL charge pump settings can be set by referring to Table 11 and Equation 3 (Charge Pump Current Calculation ) at 0334.ADV7181D_Manuals.zip

Thanks,

Poornima

Thank you for your reply.
I show you the drawing of Connection Setup.

If there are some registers that improve the SDI characteristics, it would be helpful if you could teach them.
Thank you for your support.

Hi,

  Please let us know your Encoder(DAC) part.

  Also could you please confirm these timing from EVAL ADV7181D output before giving this into PHABRIX QX.

Thanks,

Poornima

PLL jitter can also be caused by schematic implementation and layout

Encoder is ADV7341 mounted on EVAL_ADV7181D board.
The setting is also sending "SD CVBS (Address 0x56)" of "ADV7181D_ADV7181D@_ADV7341-VER.1.0c.txt".
The Jitter characteristics of Y(DAC1) measured by VM700T are shown below.
Jitter measurements are very unstable.

Best regards,

Regarding the layout of the EVAL_ADV7181D board,
The CR component connected to pin-30 (ELF) appears to be far from the terminal.
Is this layout the best pattern?

In general the ELF components should be as close to pin 30 as possible and supplied by a clean PVDD_1.8V.

Beyond that this board is a 10+ year old design and has not shown any jitter issues in the past.

There is a note in the manual "Any noise that gets onto the HS_IN input trace will add jitter to the system".  But since you are using CVBS only HS_IN should be quiet.  Out of curiosity you might try grounding HS_IN.  By default this input is left floating

The ADV7341 CLKIN_x input jitter limit is 2ns

Note CVBS jitter should be < 1ns

I'm beginning to wonder if this board has been damaged somehow.

1) Can you check the ADV7181 LLC signal for jitter . Quick check.

I measured LLC (PCLK) Clock Jitter.

Also, I changed HS_IN from open to GND connection.

However, there was no change in SDI characteristics (Timing Jitter) during GENLOCK due to CVBS

and LCC Clock Jitter characteristics.

At this point all I can suggest is there is some issue with this particular board.  Do you have access to another EVAL-ADV7181D board?

EVAL-ADV7181DEBZ is very expensive, so I only own one.
I have one EVAL-ADV7182AEBZ, so I did the same evaluation.

The result of CVBS output Jitter rampage was the same as EVAL-ADV7181D.
Also, the SDI characteristics (Timing Jitter) during genlock synchronization with CVBS did not meet the SMPTE standard, and was the same as the EVAL-ADV7181D.
Therefore, I don't think it's an issue only for the EVAL-ADV7181DEBZ that I own.
(It is very likely that other EVAL-ADV7181DEBZ will have the same characteristics.)
Could it be that the CVBS output via the ANALOG DEVICE Decoder is not suitable for SDI genlock synchronization?

Both the ADV7182 and ADV7181D implement Adaptive Digital Line Length Tracking (ADLLT) which is designed to track variable sources like VCRs.  It might be that this circuit adds some jitter noise to the output.  I have no evidence of this.

One possible test (remove input) is to set the chip in free run mode and check the output jitter again.  Not sure if will give us useful information but i would try if I had the setup here.