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ADV7181D PLL Jitter Improvement

Category: Hardware
Product Number: ADV7181D

Regarding EVAL_ADV7181DEBZ, the recommended setting (SD CVBS) of Materials (ADV7181D_ADV7181D@_ADV7341-VER.1.0c.txt) is sent and the CVBS from TSG-170D is input to get Y output.
I checked the SD/HS/3G/12G-SDI performance using this Y output (black burst signal) as a GENLOCK reference, but the SDI timing jitter exceeds the SMPTE standard values.
(PHABRIX's Qx (rasterizer) can measure it) This problem does not occur when the TSG-170D signal is used and directly input as a GENLOCK reference.

Therefore, I think I should improve the PLL clock jitter of the ADV7181D.
I wonder if there is a register to change various PLL settings in SD mode for the better jitter?
As for the resister "0x3C[2:0]: PLL_QPUMP", I tried changing it, but it didn't work very much.

on Mar 15, 2023 9:54 AM in reply to PoornimaSubramani

PLL jitter can also be caused by schematic implementation and layout

  • Encoder is ADV7341 mounted on EVAL_ADV7181D board.
    The setting is also sending "SD CVBS (Address 0x56)" of "ADV7181D_ADV7181D@_ADV7341-VER.1.0c.txt".
    The Jitter characteristics of Y(DAC1) measured by VM700T are shown below.
    Jitter measurements are very unstable.

    Best regards,

  • Regarding the layout of the EVAL_ADV7181D board,
    The CR component connected to pin-30 (ELF) appears to be far from the terminal.
    Is this layout the best pattern?

  • FormerMember
    0 FormerMember on Mar 15, 2023 9:46 PM in reply to CTCMO

    In general the ELF components should be as close to pin 30 as possible and supplied by a clean PVDD_1.8V.

    Beyond that this board is a 10+ year old design and has not shown any jitter issues in the past.

    There is a note in the manual "Any noise that gets onto the HS_IN input trace will add jitter to the system".  But since you are using CVBS only HS_IN should be quiet.  Out of curiosity you might try grounding HS_IN.  By default this input is left floating

    The ADV7341 CLKIN_x input jitter limit is 2ns

    Note CVBS jitter should be < 1ns

    I'm beginning to wonder if this board has been damaged somehow.

    1) Can you check the ADV7181 LLC signal for jitter . Quick check.

  • I measured LLC (PCLK) Clock Jitter.


    Also, I changed HS_IN from open to GND connection.

    However, there was no change in SDI characteristics (Timing Jitter) during GENLOCK due to CVBS

    and LCC Clock Jitter characteristics.

  • FormerMember
    0 FormerMember on Mar 23, 2023 12:10 PM in reply to CTCMO

    At this point all I can suggest is there is some issue with this particular board.  Do you have access to another EVAL-ADV7181D board?

  • EVAL-ADV7181DEBZ is very expensive, so I only own one.
    I have one EVAL-ADV7182AEBZ, so I did the same evaluation.

    The result of CVBS output Jitter rampage was the same as EVAL-ADV7181D.
    Also, the SDI characteristics (Timing Jitter) during genlock synchronization with CVBS did not meet the SMPTE standard, and was the same as the EVAL-ADV7181D.
    Therefore, I don't think it's an issue only for the EVAL-ADV7181DEBZ that I own.
    (It is very likely that other EVAL-ADV7181DEBZ will have the same characteristics.)
    Could it be that the CVBS output via the ANALOG DEVICE Decoder is not suitable for SDI genlock synchronization?