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Pixel port pin mappings for ADV7403 in component mode

Category: Datasheet/Specs
Product Number: ADV7403

Hi,

I have an analog component RGB video (sync on green in PAL format). I would like to digitize it in 8/10 bit ITU-R BT.656 format. From a previous query (https://ez.analog.com/video/f/q-a/565922/component-analog-rgb-sync-on-green-to-digital-itu-r-bt-656-in-adv7403), I was told that it is possible to do this. However, from the ADV7403 manuals it is said that since the inputs are RGB the component processor will be used (also evident from the configuration scripts sent). From the datasheet of ADV7403, it is mentioned that the SDP can give 8/10 bit SDR data whereas CP can only give 8/10 bit in DDR mode. But ITU-R BT.656 format is in single data rate mode. 

Please clarify if I can digitize analog RGB (PAL) into 8/10 bit SDR ITU-R BT.656 format and not DDR mode. 

Also, in the datasheet pixel port pin mapping in CP mode for 8/10 bit DDR mode is given but 8/10 bit SDR mode pin mapping is not present. Please clarify on this too. 

Regards,

Akhil

  • Hi,

     I have made some of the configuration w.r..t reference script - "RGB Sync on Green to 8 bit 656"

     Kindly do below configuration and let us know the result,

      ##SDP YPrPb##    //RGB (Please give RGB input from AIN Pins instead of YPbPt),
    :AUTODETECT YPbPr In, 10 Bit YPbPr 422 Out through Encoder:


    42 8D 83 ; Fix for Connect/Disconnect Problem
    42 00 09 ; RGB   //R on AIN1, G on AIN4, B on AIN5
    42 03 0C   8-bit@LLC1 4:2:2 ITU-R BT.656
    42 1D 47 ; Enable 28MHz Crystal
    42 27 98 ; Swap Cr & Cb & YC Delay Correction
    42 31 02 ; Clears NEWAV_MODE, SAV/EAV to suit ADV video encoders
    42 3A 11 ; set latch clock settings to 001b, Power Down ADC3
    42 3B 80 ; Enable External Bias
    42 3D A2 ; MWE Enable Manual Window
    42 3E 6A ; BLM optimisation
    42 3F A0 ; ADI Recommended
    42 86 0B ; Enable stdi_line_count_mode
    42 B4 F9 ; Fix for Connect/Disconnect Problem
    42 B5 00 ; Fix for Connect/Disconnect Problem
    42 C3 41 ; // ADC1 to Ain4, ADC0 to Ain1
    42 C4 F5;  // ADC2 to Ain5 (SOG)
    42 F3 07 ; Enable Anti Alias Filters on ADC 0,1,2
    42 F9 03 ; Set max v lock range
    42 0E 80 ; ADI Recommended Setting
    42 52 46 ; ADI Recommended Setting
    42 54 00 ; ADI Recommended Setting
    42 7F FF ; ADI Recommended Setting
    42 81 30 ; ADI Recommended Setting
    42 90 C9 ; ADI Recommended Setting
    42 91 40 ; ADI Recommended Setting
    42 92 3C ; ADI Recommended Setting
    42 93 CA ; ADI Recommended Setting
    42 94 D5 ; ADI Recommended Setting
    42 7E 73 ; ADI Recommended Setting
    42 B1 FF ; ADI Recommended Setting
    42 B6 08 ; ADI Recommended Setting
    42 C0 9A ; ADI Recommended Setting
    42 CF 50 ; ADI Recommended Setting
    42 D0 4E ; ADI Recommended Setting
    42 D1 B9 ;  ADI Recommended Setting
    42 D6 DD ; ADI Recommended Setting
    42 E5 51 ;  ADI Recommended Setting
    42 0E 00 ;  ADI Recommended Setting

    Thanks,

    Poornima

  • From which pins out of P[29:0] will I get the SDR 8/10 bit data?

    Also, 10 bit 656 is not possible?

  • Hi,

    10 bit 656 is not possible ?

           Its Possible, Please configure " 42 03 00 ; for 10 Bit Mode ".

    From which pins out of P[29:0] will I get the SDR 8/10 bit data ?

            Please refer below snap for pixel port pin out details,

    Thanks,

    Poornima

  • Thanks for the reply. 

    We have connected AIN7 = G, AIN8 = B, AIN9 = R. Since the configuration script given will not work (in the configuration script AIN7 = B, AIN8 = R, AIN9 = G), what should be the register settings for RGB with sync on green to ITU-R BT.656 SDR 8/10 bit output?