About the I2P settings of the ADV7280A.

Hi,

 Could you please ensure such issue in free run by using following register configuration values and let us know the result. 

  In this mode the ADV728x ignore the analog video input and outputs a color bars test pattern. If the issue is not present in free run then we can came to know the issue is with the analog video source or the Analog Front End of the ADV728x

 Also make sure with crystal / oscillator is outputting 28.63636MHz.

:Free-run, Color Bars 480p YPrPb Out:
delay 10 ;
42 0F 00 ; Exit Power Down Mode [ADV7280 writes begin]
42 00 07 ; ADI Required Write
42 0C 37 ; Force Free run mode
42 02 54 ; Force standard to NTSC-M
42 14 11 ; Set Free-run pattern to 100% color bars
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable INTRQ output driver
42 17 41 ; Enable SH1
42 1D 40 ; Enable LLC output driver
42 52 CD ; ADI Required Write
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write [ADV7280 VPP writes begin]
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280 writes finished]

Thanks,

Poornima

Thank you for your prompt response.

I have set the ADV7280A to the following register.

---------------------------------------------------------------------------------------------------

42 0F 00 ; Exit Power Down Mode [ADV7280 writes begin]
42 00 07 ; ADI Required Write
42 0C 37 ; Force Free run mode
42 02 54 ; Force standard to NTSC-M
42 14 11 ; Set Free-run pattern to 100% color bars
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable INTRQ output driver
42 17 41 ; Enable SH1
42 1D 40 ; Enable LLC output driver
42 52 CD ; ADI Required Write
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write [ADV7280 VPP writes begin]
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280 writes finished]

---------------------------------------------------------------------------------------------------

The encoded video was captured.
The color bar was only displayed in the upper half of the video (see attached figure).
The encoding was done in 480p30 video format.

The output frequency of crystal was 28.63636 MHz.

  see attached figure

Hi,

   FreeRun should work. Could you please crosscheck your schematics with reference one.

   Also Please refer this FAQ How Does the Free-run Mode Work in the ADV728x Devices ?

   Also let us know, Are you using any other chip other than ADV7280A to get encoded output?

Thanks,

Poornima

Hi,

   FreeRun should work. Could you please crosscheck your schematics with reference one.

   Also Please refer this FAQ How Does the Free-run Mode Work in the ADV728x Devices ?

   Also let us know, Are you using any other chip other than ADV7280A to get encoded output?

Thanks,

Poornima

Thank you for your prompt response.

Also see this FAQ How does the free-run mode of the ADV728x device work?
　We measured the following values for HS, VS, and CLK(LLC) on the ADV7280A.（Free-run, Color Bars 480p YPrPb Out）
　HS: 15.73kHz
　VS: 29.97Hz
　CLK: 27MHz

Also, can you tell me if you are using a chip other than the ADV7280A to get the encoded output?
　We are using.
　The ADV7280A output (HS, VS, CLK, Data[7:0]) is input to a SoC with Video codec function.
　The signal input from the ADV7280A is encoded by the SoC.

Thanks.

Hi,

   Could you please check the HS, VS, and CLK(LLC) values from ADV7280A for 480P60 in free run mode and compare such values with below referred image and let us know the result to segrate the issue.

Thanks,

Poornima

Hi,

For reference, could you please tell me what register settings to use to set the 480P60 free-run mode?

Thanks.

Hi,

  Could you please this entire scrpit for ":Free-run, Color Bars 480p YPrPb Out:" and compare the "HS, VS, and CLK(LLC)" values with above attached image for validating the part.

  Also Please check without I2P whether you are getting the same display problem at the output.

   Generally, "A full frame is comprised of an even and an odd field so if we are not converting the interlaced images properly into a progressive display then we might have chance to get such display with zero half field.

   Kindly note that ADV7280A will not transmit a half a field of Zeros. So Please ensure with your SoC side.

Thanks,

Poornima

Hi,

I have decoded Video timing reference codes (F,V,H) in FPGA from video signals converted by I2P function.
During the period when the V bit of the timing reference signals (TRS) was high, the H bit remained low.
Why is this?
Please see the attached image for reference.
ext_trsdec_hb_n: TRS H bit
ext_trsdec_vb_n: TRS V bit
ext_trsdec_fld_n: TRS F bit

The ADV7280A register settings are as follows.

---------------------------------------------------------------------------------------------------

42 0F 00 ; Exit Power Down Mode [ADV7280 writes begin]
42 00 07 ; ADI Required Write
42 0C 37 ; Force Free run mode
42 02 54 ; Force standard to NTSC-M
42 14 11 ; Set Free-run pattern to 100% color bars
42 03 0C ; Enable Pixel & Sync output drivers
42 04 07 ; Power-up INTRQ, HS & VS pads
42 13 00 ; Enable INTRQ output driver
42 17 41 ; Enable SH1
42 1D 40 ; Enable LLC output driver
42 52 CD ; ADI Required Write
42 80 51 ; ADI Required Write
42 81 51 ; ADI Required Write
42 82 68 ; ADI Required Write
42 FD 84 ; Set VPP Map
84 A3 00 ; ADI Required Write [ADV7280 VPP writes begin]
84 5B 00 ; Enable Advanced Timing Mode
84 55 80 ; Enable the Deinterlacer for I2P [All ADV7280 writes finished]

---------------------------------------------------------------------------------------------------

Hi,

  At first, Could you please check still you are getting that pink color issue in free run even by disabling the I2P block ?

Thanks,

Poornima

We apologize for the inconvenience.
The SoC I am using is not capable of inputting and encoding video signals for interlaced video signals.
Therefore, I am unable to check the video when I2P block is not used.
The ADV7280 is also used in our other product (network encoder).
That product does not use the I2P block function.
The pink color did not appear in the delivered video when encoded.

Hi,

  Please let us know your SoC that you are interfacing with ADV7280A ?

  Also ensure the AC coupling and Ohm load as per reference schematic which is available in design support file page.

  FreeRun should work and it doesn't work means then we may have problem with connection established between SoC & ADV7280A and also with SoC SW driver.

Thanks,

Poornima