Hi,
I have a question about a setting of TX_PLL_GEAR register (OpenLDI Tx map, Address 0x44[2:0]) of ADV7613.
The UG-907 says as follows on the page 161:
---------------------------<Begin of excerpt>---------------------------
The ADV7613 LVDS transmitter can output a maximum clock frequency of 92 MHz. The PLL gear must be set based on the output clock frequency.
This is done by setting the following control.
TX_PLL_GEAR[2:0], OpenLDI Tx, Address 0x44[2:0]
TX_PLL_GEAR[2:0] sets the PLL gear to be used based on the LVDS output clock frequency.
The ADV7613 can output graphics resolutions with clock frequency 25MHz to 92 MHz.
For this range of graphics resolutions and frequencies mentioned, the PLL gear must be set as follows:
• From 25 MHz to 40 MHz: TX_PLL_GEAR[2:0] must be set to 000.
• From 40 MHz to 92 MHz: TX_PLL_GEAR[2:0] must be set to 010.
---------------------------<End of Excerpt>---------------------------
So, the UG-907 says the TX_PLL_GEAR[2:0] should be set based on the "LVDS output clock frequency".
However, the script file "ADV7613-VER.1.1c.txt" includes following setting:
---------------------------<Begin of excerpt>---------------------------
##01 Full Scripts - HDMI Input_LVDS Output script TMDS CLK Less Than or Equal to 27MHz##
:01-03 HDMI Input_LVDS Output Port A and B:
=> This script doesn't include the setting of "C0 44" register.
so, this register keeps the default value "0x00".
##02 Full Scripts - HDMI Input_LVDS Output script TMDS CLK Greater Than 27MHz##
:02-03 HDMI Input_LVDS Output Port A and B:
...
C0 44 02 ; default 0x00, ADI Recommended write
...
---------------------------<End of Excerpt>---------------------------
So, the script says the TX_PLL_GEAR[2:0] should be set based on the "TMDS CLK".
I think that the "TMDS CLK" means HDMI input clock.
Question:
HDMI input : 1280x720p60.
ADV7613 output : Dual oLDI output.
In this case, the input and output clock frequency is as follows:
Input clock: 74.25MHz (TMDS CLK)
Output clock: 37.125MHz (LVDS output clock)
According to the UG-907, I think we should set "TX_PLL_GEAR = 000" because the LVDS output clock frequency is within from 25 MHz to 40 MHz.
According to the script, I think we should set "TX_PLL_GEAR = 010" because the TMDS CLK Greater Than 27MHz.
In this case (HDMI input : 1280x720p60, ADV7613 output : Dual oLDI output),
Which should we set "TX_PLL_GEAR = 000" or "TX_PLL_GEAR = 010"?
And which should we use the script ":01-03 HDMI Input_LVDS Output Port A or B:" or ":02-03 HDMI Input_LVDS Output Port A and B:"?
Also, I had already read a following thread:
ez.analog.com/.../344079
But the content of this thread does not answer my question.
Could you answer for my question?
Thank you!
Best regards.
Tamu
