ADV7800 PLL can't lock

Hello, I want to decode an 720p 60Hz in analogue video mode input signal, we want an 16-bit SDR Parallel output signal and we don't seem to be able to lock the PLL.

We currently had set those registers (where 0x21 is the Map IO target address on 7 bits),

i2cset -y $1 0x21 0x29 0x88  #[p.23 Tristate Control] Tristate memory interface address, control data, data strobe and data mask lines and I2c block read enable

i2cset -y $1 0x21 0x00 0x13 #[p.11 video standard] HD 1x1 720p (1280X720)
i2cset -y $1 0x21 0x01 0x01 #[p.14 primary mode] Analogue Video Modes
i2cset -y $1 0x21 0x02 0x28 #[p.15 output format 1] 16-bit and 8-bit@LLC SDR Parallel Mode
i2cset -y $1 0x21 0x04 0x28 #[p.16 output format 2] everything on default except DE on FIELD_OUT_SEL
i2cset -y $1 0x21 0x09 0x02 #[p.17 Latch clock] latch clock 010 (55 MHz to 100 MHz).
i2cset -y $1 0x21 0x0B 0x04 #[Not Referenced] DCA phase 4.
i2cset -y $1 0x21 0x10 0x90 #[p.19 Bias Current] Enable external Bias.
i2cset -y $1 0x21 0x11 0x80 #[Not Referenced] ADI Recommended.
i2cset -y $1 0x21 0x15 0x05 #[p.20 Manual PLL1 Parameter] Qpump to 101.
i2cset -y $1 0x21 0x28 0x2D #[p.22 Drive Strength] Drive strength.
i2cset -y $1 0x21 0x31 0x03 #[p.23 Sync Slicing] activate tri-level sync.
i2cset -y $1 0x21 0x38 0xB0 #[p.24 Auto CSC] enable OP_656_RANGE.
i2cset -y $1 0x21 0x53 0x86 #[Not Referenced] ADI Recommended.
i2cset -y $1 0x21 0x55 0x46 #[Not Referenced] ADI Recommended.

Here's some picture of what we see on the oscilloscope ( blue is the Y in, green is the hsync out and the red is the DE out).

picture of the Y in between two frames:

picture of the Y in on a frame:

obviously the output is not sync on the input. Can you confirm that all registers have been properly set? Any hint is welcome.

Thanks you.