The video from the stereo camera is input to the ADV7280 and processed by the Lattice CrossLink FPGA.
FPGA detects Sync Code B8 between line end and line start and judges it as a long packet.
Is it correct behavior?
I thought that long packet was only asserted when valid data.
I am attaching the oscilloscope waveform.
- h_sync : FPGA asserts from the start of synchronization pattern ‘B8 up to the last data captured before detecting LP-11 state.
- Line End : FPGA asserts when Short Packet Data Type Code=0x02
- Line Start : FPGA asserts when Short Packet Data Type Code=0x03
- ADV7280-M D0-P : ADV7280ABCPZ-M 9pin D0P signal