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Output Pixel Data in FreeRun Mode

Category: Hardware
Product Number: ADV7281A-M


I am designing a system that converts NTSC analog camera signals to MIPI with a video decoder and receives them with an FPGA.
I am using the EVAL-ADV7282AMEBZ to check the MIPI receive design of the FPGA.
The EVAL-ADV7282AMEBZ is operated in free-run mode without a camera connected.
The setting is a single color test pattern and the YCrCb value is the default (blue).
When I checked the pixel data read out by the FPGA, the Y value of the final data of all lines is different from the setting.
Is this normal?

Setting: (Y, Cb, Cr)=(0x34, 0xC0, 0x70) <---Default Value
ReadOut: (Y, Cb, Cr)=(0x01, 0xC0, 0x70)

  • Hi,

      Please let us know, Have you read this default value ((Y, Cb, Cr)=(0x34, 0xC0, 0x70) from ADV7281A-M ?

      If So for blue screen output, the default value from ADV7281M should be "Y= 0x36 , Cb = 0x0C, Cr = 0x70".



  • No, I checked the result of decoding MIPI on FPGA.
    I don't have equipment to directly observe MIPI signals.

    In all lines, all pixel data except the last pixel data read (Y, Cb, Cr)=(0x34, 0xC0, 0x70).
    Only the last pixel data of every line (Y, Cb, Cr)=(0x01, 0xC0, 0x70) is read out and the Y value is different from others.
    Regarding the MIPI decoding function of the FPGA, as a result of MIPI decoding the value of the pattern generator from the SerDes of another company that can output MIPI, the value was as expected, so I think there is no problem.

    Regarding the fact that "Y = 0x36, Cb = 0x0C, Cr = 0x70" in your answer is different from my description (Y, Cb, Cr) = (0x34, 0xC0, 0x70),
    I am referring to page 50 of UG-1176 for register addresses 0x0C and 0x0D.

    Regarding the Y value, the Functionality column of register 0x0C has the following description.
    Y[7:0] = {DEF_Y[5:0], 0, 0}
    The default value of DEF_Y[5:0] is 001101, so I read Y[7:0] = 00110100 = 0x34.

    The Cb and Cr values ​​are listed below in the Functionality column of register 0x0D.
    Cb[3:0] = (DEF_C[3:0])
    Cr[3:0] = (DEF_C[7:4])
    The default value of DEF_C[3:0] is 1100=0xC. The default value of DEF_C[7:4] is 0111=0x7.
    However, unlike the Y value, there is no description of how to add 0 when expressing Cb and Cr values ​​in 8bit (= 2-digit hexadecimal numbers).
    Potentially, the Cb value will be either 0x0C or 0xC0.
    Similarly the Cr value will be either 0x07 or 0x70.

    As mentioned above, there is no problem with the MIPI decoding function of FPGA, so I judged that (Y, Cb, Cr) = (0x34, 0xC0, 0x70) output from FPGA is correct.
    In other words, the values ​​in the 8-bit representation of the Cb and Cr values ​​were 0xC0 and 0x70, respectively, and the lower 4 bits were filled with 0. (This is analogous to the Y value case)

    Is it wrong to read the YCrCb value like this from the register value?

  • Sorry, there was a typo in my first post.
    (Cr value is also different from default)

    ReadOut: (Y, Cb, Cr)=(0x01, 0xC0, 0x70)
    ReadOut: (Y, Cb, Cr)=(0x01, 0xC0, 0x80)
  • Hi,

     Our default blue screen output value is "Y= 0x36 ,Cb = 0x0C, Cr = 0x70" as per Page 71 at ADV728x Hardware Manual

       Could you please ensure with below things,

            1.  As part of MIPI specification, the MIPI receiver needs to terminate the signals correctly. The termination required changes depending on the MIPI mode (e.g. High speed, Low power mode etc). The receiver needs to detect the mode of operation and dynamically set its termination accordingly. Note that the Clock signals will only appear correctly when properly terminated.

             When we try to terminate the output signals from the ADV7280-M (Microprocessor / FPGA) then you will see the correct MIPI traces.

              Note that the Microprocessor / FPGA needs to be able to detect the output format (high speed mode or low power mode) and dynamically change its input impedance. If the Micro processor/ FPGA does not control the termination correctly then the MIPI signals from the ADV7280-M cannot be decoded.

              For our evaluation of the ADV7280-M we used the MIPI reference termination board which is available from here:

              MIPI Test Boards | Interoperability Laboratory

          2. Also If the MIPI CSI-2 receiver is initialized after the transmitter device is initialized, the MIPI CSI-2 may never detect the LP to HS mode transition.

                  Some MIPI CSI-2 receivers wait for an LP to HS mode transition on the MIPI CSI-2 clock lane before starting video capture.
                  However, the LP to HS mode transition on the MIPI CSI-2 clock lane occurs only once on the ADV728x-M, ADV728x-MA immediately after they are initially programmed.
                  If the MIPI CSI-2 receiver is initialized after the transmitter device is initialized, the MIPI CSI-2 may never detect the LP to HS mode transition
       on the clock lane from the transmitter device. If the MIPI CSI-2 receiver does not detect the LP to HS mode transition, it may never start video capture.
    Note : To overcome this issue, manually program the clock lane of the ADV728x-M,ADV728x-MA, or ADV7282-M to enter and then exit LP mode.
    The easiest way to do this is by toggling the CSITX_PWRDN bit (Address 0x00, Bit 7).The MIPI CSI-2 receiver then recognizes an LP to HS mode transition and begins video capture.

                 And also expert captured the MIPI packet output from the ADV7280-M in free-run mode using a Keysignt U4421A MIPI protocol analyzer. The captured MIPI packets are available on engineering zone at "".