EVAL-ADV7182AEBZ_HSYNC_VSYNC_Abnormal Timing

Dear GuenterL-san,

CC:  Poornima-san,

Thank you for your advise.

Could you please try to check this symptom with Step1 to 6 on EVAL-ADV7182AEBZ?

We think that you don't check this symptom on EVAL-ADV7182AEBZ.

Thanks and Best regards

Isshin Kida

Hi IsshinKida San,

       For our Analog device evaluation boards, a Golledge MA01377 crystal is used. Please refer this FAQ about the Golledge crystal attachment at Notes about the crystal needed for the ADV7180 or ADV7182 - Documents - Video - EngineerZone (analog.com) -   Most of our testing is done with the attached crystal.  

       C2 & C3 are dependent on the load capacitance specified in the crystal data sheet.  As an example, a Golledage MA01377 has a load capacitance of 30pF so C2 = C3 = 2 * (30 - 2) - 4 = 52pF, closest real cap. value would be 47pF. Please see our reference schematic (Marked in Yellow Color).

        And these caps adjust the impedance the crystal drivers see to make sure the crystal will oscillate.

Thanks,

Poornima

Dear Poornima-san,

Thank you for your support and comment.

We refer crystal load capcitance value. And we review crystal load capacitance value.

Please tell us again.

Does it happen this symptom if cystal load capacitance is wrong?

We think that if crystal doesn't work well, it happen other symptom, for example no output DCLK and abnormal DCLK waveform.

But as this waveform, this symptom is Vsync delay.

Thanks and Best regards

Isshin Kida

OK, lets break this up into 2 parts.

Part 1, the crystal.  For proper operation the crystal circuit needs the correct load caps to balance the rest of the oscillator circuit in the chip.  If the load caps are incorrect the crystal may not oscillate at all or possibly at the wrong frequency.  If you probe either side of the crystal the probed capacitance can affect the oscillation operation.  If the load caps are temperature sensitive then it can affect the oscillation.  This is why load caps are always C0G (NPO) material, better temp coefficients.  

Part 2, 2 clock offset.  

   a) First of all I'd like to see a scope trace of Ain1, VS and HS.  Is anything changing with the source.

   b) I'm a bit confused by the statement 'reading the script file'.  The script files are are write only to the ADV7182.  Normally you'd only be reading something back is if your controller is trying to read back what the auto-detect setting are.  

   c) I assume the 2 clock offset stays consistent after you do the first scope capture and it doesn't revert back to a good case.

   d) is there any change while doing the I2C writes, you are coupling noise into Ain1 messing with the sync pulses?

   e) Even if the sync pulse timing changes a bit can not the downstream device handle it.  What truly makes it a good or bad case as long the the timing is consistent.

Poornima, do you have a setup to duplicate this issue? 

Hi Guenter,

       Sorry, Here we don't have ADV728x based eval board.

Thanks,

Poornima

Dear Guenter-san and Poornima-san,

Thank you for your reply.

-If we can send you EVAL-ADV7182AEBZ, can you try to duplicate this symptom?

-Noted, Part1,

-About Part2,

a) First of all I'd like to see a scope trace of Ain1, VS and HS. Is anything changing with the source.
--> We tried to change some source. It also happne this symptom.
b) I'm a bit confused by the statement 'reading the script file'. The script files are are write only to the ADV7182. Normally you'd only be reading something back is if your controller is trying to read back what the auto-detect setting are.
-->Sorry,I confused you. 'reading the script file' is mistook, correct operaion is "Write the script file".
c) I assume the 2 clock offset stays consistent after you do the first scope capture and it doesn't revert back to a good case.
-->Yes, your understanding is correct.
d) is there any change while doing the I2C writes, you are coupling noise into Ain1 messing with the sync pulses?
-->We don't change anythin whilw doing I2C write.
e) Even if the sync pulse timing changes a bit can not the downstream device handle it.
What truly makes it a good or bad case as long the the timing is consistent.
--> This symptom problem is unstable V-sync.
If Sync is unstable, video image position is shifted.

Thanks and Best regards

Isshin Kida