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EVAL-ADV7182AEBZ_HSYNC_VSYNC_Abnormal Timing

Category: Software
Product Number: ADV7182
Software Version: DVP Eval Latest Source 10-14-11.exe

Dear Sirm,

We use DVP Eval Latest Source 10-14-11.exe on EVAL-ADV7182AEBZ.

It happen the following symptom.

<Symptom Detail>

AN1/Input Format:  NTSC 

Using Script File:Scripts-> ADV7182A_CUST->02_CVBS_SINGLE_ENDED_AUTODETECT->Autodetect_CVBS_Single_Ended_In_Ain_1_YPbPr_Out

We checked Hsync and Vsync pin by oscilloscope.

-It  sometimes happen abnormal of the rising timing of HSYNC and VSYNC (it sometimes work normally.)

 It is unstable behavior of VSYNC.

   -Normal case : VSYNC is same rising timing as HSYNC. (HSYNC and VSYNC rise at same time.) 

   -Abnormal case : VSYNC is different rising timing,shiftted(delayed) by 2 clock from HSYNC.

 At reading timing of the script file, it may be normal or abnormal. (dependent on read script file timing)

Could  you please advise us about this symptom?

Thanks and Best regards

Kida

 

Parents
  • Hi Isshinkida San,

          Generally, the timing of the HSync/VSyncs are determine what is blanking and what is active video, basically the state of VSync when there is an HSYNC transition determines whether the change is to active video or blanking and 'Vsync' to be low only when any format change.

            Please note that, We can have the certain possibilities for HSYNC/VSYNC Abnormality.

                  1. There might be a problem with crystal frequency ( Is it 28Mhz or 28.63636Mhz? It has to be the right frequency.  The offset is definitely a problem as well-- if you are using the same bias circuit as the eval board it should be the same offset.  You should probably check the components in that circuit and check for shorts.

                  2.  The PLL filter/Power supply is the most likely be an problem (PLL (PVDD) power supply might be an noisy ).

         .        3. Please ensure with source, for example If the source is inputting a strange Vsync timings then this timing and that will be reflected through the entire path. (Hsync and Vsync are encoded in the same symbol in the input video stream.  Therefore they should be whatever the source is outputting).

    Note:  

    H & V Sync timings are all based on the VESA, SMPTE or CEA standards depending on the resolution. So the respective resolution timing details we can get it from standards specification.

    These details we need to look at the timing specifications from CEA861-E or any other reference document like Video Demystified book ( video-demy5.pdf ) .


    Thanks,

    Poornima

  • Dear Poornima-san,

    Thank you for your reply and support.

    This symptom happen on  EVAL-ADV7182AEBZ with script file ,ADI evaluation board and provided software.

    Therefore we think that  the crystal frequency ,power supply filter and register setting are no problem.

    We will check to happen dependent on input source.

    We have one more question.

    Are there posibility that H/Vsync happen synchronization error change  by register setting timing?

    For example, input signale then setting resiter. Setting resiter then input signal.

     At writing to the script file, the symptom is chanded normal or abnormal behavior (it is dependent on writing script file timing)

    Thanks and Best regards

    Isshin Kida

     

  • Dear Poornima-san,

    Thank you for your reply.

    >>Step5:  Load Script file"Autodetect_CVBS_Single_Ended_In_Ain_1_YPbPr_Out"

    >>Step6: Run Script file

    >>--> Don't Repeat Step5 and Step6 .

    We excuted Step1 to Step5 only.

    As result, it  happen Vsync deleyed, same symptom at half the chance.

    (it doesn't happen happen Vsync deleyed, same symptom at half the chance.)

    It seems that this symptom is dependent on reading Script file timing.

    Thanks and Best regards

    Isshin Kida

  • Hi IsshinKida San,

           As per your comment, Issue is still exist even when you do not repeat the step 5 and step 6 continuously. Is my understanding correct?

          The reason i told too don't repeat 'Step 5 and 6' because once we run the script the register configuration remain persist until we power off the board.

     Thanks,

     Poornima

  • Dear Poornima-san,

    Yes,your undestanding is correct.

    As result, this issue is dependent on reading "Script file" timing.

    But we don't know which registers affect it.

    Please advise us which register might be related with this issue if possible.

    Thanks and Best regards

    Isshin Kida

  • Hi,

       I don't think the register will affect this abnormal scenario.

       If possible, Could you please check the same in different eval board.

    Thanks,

    Poornima

  • Dear  Poornima-san,

    Thank you for your reply.

    We tried the different PCBA (by ourselves design) with ADV7182A.

    It also happen same symptom.

    Please tell us about evaluation schematics "adv7182a-adv7280a-32ebz-sch_a.pdf" around X'tal "ABM8AIG-28.63636MHz-12-2Z-T3"

    We think that "-12" of "ABM8AIG-28.63636MHz-12-2Z-T3"  means "Load Capacitance (pF)" on the datasheet

    (ABM8AIG-1775167.pdf)

    But there is 20pF "Load Capacitance (pF)"  on Evalution board schematics.

    (1) Is "Load Capacitance (pF)" around X'tal schematics corret?

    (2) Is this X'tal of "Load Capacitance (pF)"  related with this symptom?

    Thanks and Best regards

    Isshin Kida

  • FormerMember
    0 FormerMember
in reply to IsshinKida

.PDF

Crystal load caps are calculated from crystal parameters outlined in this app note, see Figure 4 and the formulas in that paragraph.  From my calculation the load caps should be ~14pf however 20pF is close enough to start the crystal oscillator.  I don't know the parasitic capacitance for the EVAL board.

  • Dear GuenterL-san,

    CC:  Poornima-san,

    Thank you for your advise.

    Could you please try to check this symptom with Step1 to 6 on EVAL-ADV7182AEBZ?

    We think that you don't check this symptom on EVAL-ADV7182AEBZ.

    Thanks and Best regards

    Isshin Kida

  • Hi IsshinKida San,

           For our Analog device evaluation boards, a Golledge MA01377 crystal is used. Please refer this FAQ about the Golledge crystal attachment at Notes about the crystal needed for the ADV7180 or ADV7182 - Documents - Video - EngineerZone (analog.com) -   Most of our testing is done with the attached crystal.  

           C2 & C3 are dependent on the load capacitance specified in the crystal data sheet.  As an example, a Golledage MA01377 has a load capacitance of 30pF so C2 = C3 = 2 * (30 - 2) - 4 = 52pF, closest real cap. value would be 47pF. Please see our reference schematic (Marked in Yellow Color).

            And these caps adjust the impedance the crystal drivers see to make sure the crystal will oscillate.

    Thanks,

    Poornima

  • Dear Poornima-san,

    Thank you for your support and comment.

    We refer crystal load capcitance value. And we review crystal load capacitance value.

    Please tell us again.

    Does it happen this symptom if cystal load capacitance is wrong?

    We think that if crystal doesn't work well, it happen other symptom, for example no output DCLK and abnormal DCLK waveform.

    But as this waveform, this symptom is Vsync delay.

    Thanks and Best regards

    Isshin Kida

  • FormerMember
    0 FormerMember in reply to IsshinKida

    OK, lets break this up into 2 parts.

    Part 1, the crystal.  For proper operation the crystal circuit needs the correct load caps to balance the rest of the oscillator circuit in the chip.  If the load caps are incorrect the crystal may not oscillate at all or possibly at the wrong frequency.  If you probe either side of the crystal the probed capacitance can affect the oscillation operation.  If the load caps are temperature sensitive then it can affect the oscillation.  This is why load caps are always C0G (NPO) material, better temp coefficients.  

    Part 2, 2 clock offset.  

       a) First of all I'd like to see a scope trace of Ain1, VS and HS.  Is anything changing with the source.

       b) I'm a bit confused by the statement 'reading the script file'.  The script files are are write only to the ADV7182.  Normally you'd only be reading something back is if your controller is trying to read back what the auto-detect setting are.  

       c) I assume the 2 clock offset stays consistent after you do the first scope capture and it doesn't revert back to a good case.

       d) is there any change while doing the I2C writes, you are coupling noise into Ain1 messing with the sync pulses?

       e) Even if the sync pulse timing changes a bit can not the downstream device handle it.  What truly makes it a good or bad case as long the the timing is consistent.

    Poornima, do you have a setup to duplicate this issue? 

  • Reply
    • FormerMember
      0 FormerMember
    in reply to IsshinKida

    OK, lets break this up into 2 parts.

    Part 1, the crystal.  For proper operation the crystal circuit needs the correct load caps to balance the rest of the oscillator circuit in the chip.  If the load caps are incorrect the crystal may not oscillate at all or possibly at the wrong frequency.  If you probe either side of the crystal the probed capacitance can affect the oscillation operation.  If the load caps are temperature sensitive then it can affect the oscillation.  This is why load caps are always C0G (NPO) material, better temp coefficients.  

    Part 2, 2 clock offset.  

       a) First of all I'd like to see a scope trace of Ain1, VS and HS.  Is anything changing with the source.

       b) I'm a bit confused by the statement 'reading the script file'.  The script files are are write only to the ADV7182.  Normally you'd only be reading something back is if your controller is trying to read back what the auto-detect setting are.  

       c) I assume the 2 clock offset stays consistent after you do the first scope capture and it doesn't revert back to a good case.

       d) is there any change while doing the I2C writes, you are coupling noise into Ain1 messing with the sync pulses?

       e) Even if the sync pulse timing changes a bit can not the downstream device handle it.  What truly makes it a good or bad case as long the the timing is consistent.

    Poornima, do you have a setup to duplicate this issue? 

    Children in reply to IsshinKida

    Part 2d)  If the I2C traces on the board run close to the AIN1 trace you might electrically couple noise from the I2C lines into the analog signal.   I was wondering if these transitions were interfering with the video syncs.  If the Vsync had noise on it then only duration of the I2C writes would. The fact that it remains unstable indicates it's not an interference problem.

  • Dear GueterL-san,

    Thank you for your support about this issue.

    We will get another EVK-ADV7182A this week.

    But we coudn't get this Software "DVP EVAL Software on your web site.

    There are no link on DVP EVAL Software.

    Which web site can we download this software?

    - --> I found the same FAQ on web site. I can install it by myselef.

    After another EVK,  I will ask again.

    Thanks and Best regards

    Isshin Kida