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ADV7281-M Video issue

Category: Software
Product Number: ADV7281AWBCPZ-M

   abnormal                                                                                   normal

We developing a product using the ADV7281AWBCPZ-M.

We convert analog video input to MIPI and output it.

It is causing the phenomenon that the even and odd of the interlace are reversed.

This phenomenon occurs when the analog video input is turned on and off, and does not always occur.

Any advice would be appreciated.

Thanks

Parents
  • Hi,

    Please note that, when analog video source is quickly disconnected and then reconnected(i.e Turn On and Off), then the ADV7180/ADV7182/ADV728x can output a field of non-standard length. This can confuse some back end processors. Resulting in unusual output video for 2 or 3 frames of video.

    The ADV7180/ADV7182/ADV728x locks to an analog video source at random positions. i.e. The ADV7180/ADV7182/ADV728x can lock to an video source in the middle of a frame of video. This would result in the first frame being shorter than usual. This could confuse the back end processor and result in video defects.

     In that case only way to prevent this issue occurring is to modify the software code in the back end processor. The back end processor should wait until the IN_LOCK bit of the ADV7180/ADV7182/ADV728x has gone high. The back end processor should then wait until start of the next frame of video before displaying the output from the ADV7180/ADV7182/ADV728x.

     Another option is to implement a line counter in the frame buffer in the back end processor. This is a piece of code that counts the lines output from the ADV7180/ADV7182/ADV728x. This will prevent unusual length frames being output.

     Please double check that the backend processor is configured correctly with latest software.

     Also ensure with register 0x5B as 0x80 for interlaced format (i.e Advanced timing mode must be enabled in order for the I2P converter to work correctly). Please refer below snap.

    Thanks,

    Poornima

  • Dear Poornima

    Thank you for advice.
    We modified the backend processor software to wait until the IN_LOCK bit goes high after analog video source Turn On and Off.
    However, the phenomenon could not be improved.

    Also, the ADV72810-M that we are using does not have an I2P converter, so there was no 0x5B setting.

    By the way, EVEN_FIELD at 0x45 in your snap, which doesn't lock to "0" or "1" after IN_LOCK bit goes high. Is this correct?

    Thanks,

    Iwasaki

  • Hi,

    By the way, EVEN_FIELD at 0x45 in your snap, which doesn't lock to "0" or "1" after IN_LOCK bit goes high. Is this correct?

       Are you trying to set this EVEN_FIELD register or Are you getting any invalid value from this register ?

    Also Please let us know, How you are saying that the even and odd of the interlace video are reversed. How you are confirming that?

    Also let us know, What type of image difference are you getting when interlace video are reversed. We are not able to see any difference from the attached image.

    Thanks,

    Poornima

  • Dear Poornima

    Thank you for your quick reply.

    >Are you trying to set this EVEN_FIELD register or Are you getting any invalid value from this register ?
    -->The getting value cannot be determined. This register is read-only and is not set.


    >Also Please let us know, How you are saying that the even and odd of the interlace video are reversed. How you are confirming that?
    -->We think from the output image by the backend processor.And attached a expanding image and our thoughts.


    Thanks,

    Iwasaki

  • Hi,

    We can determine the Odd/Even field by using the F bit,

    For example, for interlaced input the F bit will change between 0 and 1 to indicate if the field is an odd or even field. The information can then be seen in the frame numbers in the Frame Start and Frame End packets in the MIPI output of the ADV728x.

    In Interlaced mode, the even odd field information is included in embedded in the digital synchronization signals.
    It is also possible to use the VS/FIELD/SFL pin to determine even/odd fields. In interlaced mode, the VS/FIELD/SFL pin is programmed to output field synchronization pulses.

    Also from your above shared image it seems like some artifacts.

     1.Modify some of the 2D comb filter registers in the ADV7281-M and try to minimize the artifacts in your system.
     Try reading the Chroma filter, Luma Filter, Chroma Transient Improvement, Digital Noise Reduction and Luma   Peaking Filter, and Comb filter sections of the ADV7182A datasheet. You may get some improvement.

     2. Please configure according to the script exactly and let us know whether you got some improvement at 5545.ADV7280M_Cust-VER.4.1.txt.zip

     3. Have you tried with different sources?

     4. Also ensure with below things,

         a) Make sure whether ADV7281-M is programmed correctly with ADI recommended I2C writes,

         b) Could you ensure that during power-up: the reset pin is held low for at least 5ms after the 3.3V, 1.8V and powerdown lines go high. After the reset pin goes high, wait for at least 5ms before starting I2C communication.

          Expert written an application note describing the main issues interfacing the ADV728x with a MIPI receiver. Please refer the link here: https://www.analog.com/media/en/technical-documentation/application-notes/AN-1337.pdf

    Thanks,

    Poornima

  • Dear Poornima

    Thank you for your advice.

    > 1.Modify some of the 2D comb filter registers in the ADV7281-M and try to minimize the artifacts in your system.
    Try reading the Chroma filter, Luma Filter, Chroma Transient Improvement, Digital Noise Reduction and Luma Peaking Filter, and Comb filter sections of the ADV7182A datasheet. You may get some improvement.
    -->Thanks, We will try them.

    > 2. Please configure according to the script exactly and let us know whether you got some improvement at 5545.ADV7280M_Cust-VER.4.1.txt.zip
    -->We were setting based on ADV7281M_Cust-VER.4.5.txt. and We tried with 5545.ADV7280M_Cust-VER.4.1.txt, but the phenomenon did not change.

    > 3. Have you tried with different sources?
    -->We have tried it on multiple devices. and We have also tried with NTSC and PAL devices.

    > 4. Also ensure with below things,
    a) Make sure whether ADV7281-M is programmed correctly with ADI recommended I2C writes,
    -->We are using the I2C write access implemented in the kernel.org driver code linked from ADI's HP.
    b) Could you ensure that during power-up: the reset pin is held low for at least 5ms after the 3.3V, 1.8V and powerdown lines go high. After the reset pin goes high, wait for at least 5ms before starting I2C communication.
    -->The driver is configured to wait 5ms before and after reset release.

    Thanks,

    Iwasaki

  • Hi,

      If Possible, Could you please share your register configuration with us?

      Please note that, When you terminate the output signals from the ADV7280-M (in a micro processor/ FPGA) then only you will see the correct MIPI traces. Note that the Micro processor/ FPGA needs to be able to detect the output format (high speed mode or low power mode) and dynamically change its input impedance. If the micro processor/ FPGA does not control the termination correctly then the MIPI signals from the ADV7280-M cannot be decoded properly. This has been described in the applications note AN-1337.

      However unless the MIPI signals are terminated properly you will not be able to definitively state if the MIPI signals are correct or if some other issue is occurring (e.g. Noise coupling onto MIPI traces).

      If the back-end processor is terminating the MIPI signals correctly then you should see correct MIPI signals (like those seen in figure 2 of AN-1337).

      Until proper termination is achieved then you will not be able to decode video data properly from the MIPI CSI-2 signals output by the ADV7280-M.

      For our evaluation of the ADV7280-M we used the MIPI reference termination board available from here:

      MIPI Test Boards | InterOperability Laboratory

    Thanks,

    Poornima

  • Dear Poornima

    Thank you for your advice.

    >If Possible, Could you please share your register configuration with us?
    -->Our register configuration is as follows.
    42 0F 00 ; Exit Power Down Mode
    42 00 00 ; INSEL = CVBS in on Ain 1
    42 0E 80 ; ADI Required Write
    42 9C 00 ; ADI Required Write
    42 9C FF ; ADI Required Write
    42 0E 00 ; Enter User Sub Map
    42 03 4E ; ADI Required Write
    42 04 57 ; Power-up INTRQ pin
    42 13 00 ; Enable INTRQ output driver
    42 17 41 ; select SH1
    42 1D C0 ; Tri-State LLC output driver
    42 52 CD ; ADI Required Write
    42 80 51 ; ADI Required Write
    42 81 51 ; ADI Required Write
    42 82 68 ; ADI Required Write
    42 5D 1C ; Enable Diagnostic pin 1 - Level=1.125V
    42 5E 1C ; Enable Diagnostic pin 2 - Level=1.125V
    42 FE 88 ; Set CSI Map Address
    88 DE 02 ; Power up MIPI D-PHY
    88 D2 F7 ; ADI Required Write
    88 D8 65 ; ADI Required Write
    88 E0 09 ; ADI Required Write
    88 2C 00 ; ADI Required Write
    88 00 00 ; Power up MIPI CSI-2 Tx

    And we were able to solve the abnormal display by adding the following register configuration.

    [VPP Map]
    42 FD 84 ; Set VPP Map Address
    84 A3 00 ; ADI Required Write
    84 5B 00 ; Advanced Timing Enabled
    84 55 80 ; Enable I2P
    [MIPI CSI-2 Tx Map]
    88 01 20 ; ADI Required Write
    88 02 28 ; ADI Required Write
    88 03 38 ; ADI Required Write
    88 04 30 ; ADI Required Write
    88 05 30 ; ADI Required Write
    88 06 80 ; ADI Required Write
    88 07 70 ; ADI Required Write
    88 08 50 ; ADI Required Write
    88 1D 80 ; ADI Required Write

    Do you know why?

    MIPI signals will be confirmed later.

    Thanks,

    Iwasaki

  • Dear Poornima

    Thank you for your advice.

    We are also making image improvements.
    What it does is remove the black band at the top of the image.
    We tried changing 0x04 (Extended output control) to 0xD7 (bit 7 BT.656-4 set) referring to other Q&A.
    Then the black band became a little narrower but could not be removed.
    Any advice to remove it ?

    Thanks,

    Iwasaki

  • Hi,

    Could you please try disabling the ACE feature by writing 0x00 to User Sub map 2, register 0x84 .

    Please make sure with crystal clock (i.e) Make sure you are providing correct XTAL 28.6363,and your script selects 28.63636 crystal
    Also PVDD is very important for maintaining the Video stability.
    Ideally it should be ferrite bead isolated from other supplies and the data sheet reference schematic does not show this which is OK if the PVDD source is very clean.
    First check PVDD noise both high frequency and lower frequencies around the horizontal rates. If noise is coupled into PVDD then the PLL might lose lock and causing image issues.

    Thanks,

    Poornima

  • Dear Poornima

    Thank you for your advice.

    >Could you please try disabling the ACE feature by writing 0x00 to User Sub map 2, register 0x84 .
    -->We tried it, but the phenomenon did not change.

    >Please make sure with crystal clock (i.e) Make sure you are providing correct XTAL 28.6363,and your script selects 28.63636 crystal
    -->It's OK.

    >Also PVDD is very important for maintaining the Video stability.
    -->PVDD source is clean.

    According to the datasheet, the output resolution is 720x487 for NTSC.
    Our analog source is 720x480.
    We consider 487-480=7(line) to be the black band.
    Is this understanding correct?

    If so, is it possible to change the output resolution to 720x480?
    Or is it possible to move the black band to the bottom of the image?

    Thanks,

    Iwasaki

Reply
  • Dear Poornima

    Thank you for your advice.

    >Could you please try disabling the ACE feature by writing 0x00 to User Sub map 2, register 0x84 .
    -->We tried it, but the phenomenon did not change.

    >Please make sure with crystal clock (i.e) Make sure you are providing correct XTAL 28.6363,and your script selects 28.63636 crystal
    -->It's OK.

    >Also PVDD is very important for maintaining the Video stability.
    -->PVDD source is clean.

    According to the datasheet, the output resolution is 720x487 for NTSC.
    Our analog source is 720x480.
    We consider 487-480=7(line) to be the black band.
    Is this understanding correct?

    If so, is it possible to change the output resolution to 720x480?
    Or is it possible to move the black band to the bottom of the image?

    Thanks,

    Iwasaki

Children
  • Hi,

       If so, is it possible to change the output resolution to 720x480 ?

         No, It's not possible to change the output resolution to 720x480. All ADV728x output video timing is compliant with the ITU-R BT.656-3 or ITU-R BT.656-4 standards.

         Could you please try with below register for image shipment.

    Please note, In interlaced mode, an NTSC video source results in the ADV7280-M, ADV7281-M, ADV7281-MA, and ADV7282-M transmitter devices outputting video where the odd fields are one line longer than the even fields.
     This difference occurs with NTSC sources only. PAL sources result in even and odd fields of the same length. For more information Please refer Application Note 1337.
              In NTSC mode the ADV7280-M outputs a 60 Hz field rate so please check your TV screen whether that is match with 60Hz or 50Hz.

    Thanks,

    Poornima 

  • Dear Poornima

    Thank you for your advice.

    We couldn't solve the interlace problem, so we are thinking of changing from ADV7281-M to ADV7282-M and using built-in I2P.
    And about the black band, we are thinking about masking it with the image sensing interface.

    However, using I2P in the ADV7282-M causes vertical jitter.
    This happens even in free-run mode (Boundary Box Test Pattern).
    Is there any advice to solve this phenomenon?

    Thanks,

    Iwasaki

  • Hi,

     Please refer below expert comments to get rid of the I2P artifacts,

      There are two possible causes of these artifacts: Interlaced to Progressive conversion artifacts or 2D comb artifacts.

    Interlaced to progressive conversion:

    The I2P block of the ADV728x works by storing a few lines of video. e.g. lines 1, 3, 5 on an odd field. It will then interpolate between these lines to generate the missing lines e.g. it will interpolate for lines 2 and 4.

    The I2P does contain a smoothing filter to minimize artifacts but some artifacts can still occur.

    2D Comb:

    The ADV7180/ADV7182/ADV728x video decoders are designed to be low cost analog to digital video decoders and as such they only have 2D comb YC separation filters.

    2D comb filters are good at separating the luma and chroma information but artifacts such as the one you have highlighted are still possible.     

    Solutions :

    1) Use a deinterlacer in your back end processor rather than using the I2P block of the ADV7280. The backend processor will have to store an odd frame of video in a buffer, then store an even frame of video and then stitch these two frames together to generate a progressive field. This will minimize interlaced to progressive errors but will add a delay to your system.

    Be sure to introduce a line counter or similar software control to ensure that you do not get buffer overflows.

    2) Modify some of the registers in the ADV7280 to try and minimize 2D comb this artifacts for your system.

         Try reading the Chroma filter, Luma Filter, Chroma Transient Improvement, Digital Noise Reduction and Luma Peaking Filter, and Comb filter sections of the ADV728x hardware manual. You may get some improvement but you will never be totally able to remove 2D comb artifacts.

    Note: The ADV7186 part can perform frame based deinterlacing which should avoid the artifacts that you see with the ADV7280 (the ADV7280 uses line based deinterlacing).

    Note the tradeoff here is that the ADV7186 is more expensive and complex than the ADV7280. Also the frame based deinterlacing will generate a significant latency through the system. This is usually not desirable for automotive safety applications.

    Kindly refer below post on how to modify the boundary box test pattern,

    boundary box test pattern can't  be complete display

    In interlaced mode the boundary box test pattern top line appears on odd fields and bottom line appears on even fields.

    In interlaced mode the first/last pixel on every second line in the odd and even fields are white to generate the white vertical lines.

    In progressive mode the line interpolation algorithm doubles the size of the odd and even fields. Therefore the first frame could be doubled odd field that will only have the white line at its top. The next frame could be doubled even field that will only have the white line at its bottom.

    Thanks,

    Poornima