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ADV7513 I2S No Audio

Category: Hardware
Product Number: ADV7513

Hi all,

Happy new year! Hoping someone on here can point me in the right direction as I have a feeling I must be doing something wrong...I have a project where I am pulling audio and video from a PS2 console, passing into an FPGA, upscaling & de-interlacing the video to 1080p, 60Hz then outputting to an ADV7513 and over HDMI to the screen.

The video aspect is working perfectly, no issue at all, both when the FPGA is doing heavy lifting and outputting at 1080p or when I set the FPGA to act as a simple pass-through and the video stream is the default 576i from the console. Obviously I adjust the registers within the ADV7513 accordingly for 1080p vs 576i, but I get a proper video signal on screen every time.

The issue is with the audio aspect. The console feeds the audio as I2S format to a DAC and this is where I am tapping into the audio stream, details of which are as follows...

  • LRCLK = 48kHz
  • MCLK = 18.43MHz (384x LRCLK)
  • SCLK = 3.07MHz

From the screen captures below I took from my logic analyser the I2S format appears to be 'Left Justified' and 24-bits wide as shown in Fig 17 of the ADV7513 programming guide (snippet in the 4th image).[

As such, I setup the ADV7513 audio registers as follows (based on info from page 69 to 80 of the Programming User Guide)...

  • Register 0A set to binary value 00000010 / hex value 02 (Auto CTS, I2S data stream & 384x MCLK ratio)
  • Register 0B set to binary value 01101110 / hex value 6E (SPDIF disabled, I2S clock latches on falling edge (see images above) and MCLK is available (not internally generated))
  • Register 0C set to binary value 00000110 / hex value 06 (Use I2S stream sampling frequency, use channel status bits from I2S stream, only I2S pin 0 enabled and left justified mode (based on screen captures above)
  • Register 15 set to binary value 00100000 / hex value 20 (I2S sampling frequency of 48kHz)

The last register (0x15) should not be needed as I have set register 0x0C to use the I2S stream sampling frequency, but I have tried with register 0x15 set and not set, makes no difference.

Despite configuring the registers seemingly correctly there is still no audio at all. I have tested both with the 1080p video feed and the un-tampered 576i video feed in case there was some mismatch preventing it from working. The monitor I am connected to has audio volume set to 50% and outputs audio fine when connected to my laptop.

Link to programming guide for reference...

Anyone have any suggestions?

Fixing image link errors
[edited by: Mario87 at 1:48 PM (GMT -5) on 3 Jan 2023]
  • Ok, so looks like I may have forgotten to set register 0x02 with value 6144 (decimal) / 0x18 (hex). This is the N-parameter register and used to configure the audio clock regeneration at the sink. So now audio works with my 576i pass-thru config quite well (clear audio), but when I use my 1080p config to upscale, de-interlace, etc the audio is crackling and comes / goes.

    Anyone have any thoughts on what might be happening here? With my 1080p FPGA config the audio is still just passed through at the moment, exactly as it is on the 576i config, just goes into the FPGA and straight out, so not sure why the different video stream is affecting the audio from working properly at 1080p?

    Is 48kHz not a supported sampling frequency for HD video? Do I need to increase the sampling frequency up to 192kHz (4x) using a PLL or similar within the FPGA?

  • Hi,

    Please refer HDMI 14b specification, Section” Audio” to know more details about Audio clock regeneration. The recommended N and expected CTS values for several standard TMDS clock rates are listed down in Table 7.1, 7.2 and 7.3.

    We have verified our evaluation platform by inputting different audio input sample frequencies like 32 kHz, 44.1 kHz, 48 kHz, 88.2 kHz, 96 kHz, 176.4 kHz, 192 kHz using script and software driver and found the N and CTS values are updated correctly in the HDMI Protocol analyzer which is same as per the HDMI specifications as reference.

    Please note that you have to tweak N and CTS values to get good audio out.
    Moreover, it is good to use HDMI generator and analyzer for initial development and this would be helpful for debugging the HDMI audio projects

    Please try with below reference script

    :6-4b - 1920 x 1080p60, YPrPb 444 in, YPrPb 444 out, 48kHz 8 Ch VIC 16:

    The writes to address 72 are the writes to the ADV7511 which should work just fine for the ADV7513 since they are basically the same part expect package size.  

    Also refer section Recommended N and Expected CTS Values at ADV7511W Programming Guide



  • Thanks, however I think I might know what I need to do in order to fix it, although I am not entirely sure of the cause for it...basically I have a custom test board with headers that I can probe the signals from, so I started probing them and I noticed if I probe the MCLK or SCLK lines the audio improves, not perfect, but it improves, then I noticed if I squeeze the test header with my fingers the audio becomes perfect!

    It must be the extra capacitance from my body / the probes which is making it work, but what I do not understand is why does it only need this extra capacitance on the audio lines if the video feed is at 1080p. Is the fact the FPGA is running at higher clock speeds (2.75x faster for the clock and around 11x faster for each of the 24-bit video signals) meaning that it's in turn consuming more power and not able to provide such a stable output on the audio lines?

    It is a Nexys Video dev board with Artix-7 FPGA and all my signals (24-bit video, H-Sync, V-Sync, FID, H-Blank, V-Blank, I2S Audio, etc) all feed into FPGA banks 15 & 16 (due to how the dev board is designed and the need to use the FMC connector I can't really use other banks).

    Is it simply too much for just those 2 banks to handle in a stable manner when having to deal with the video at higher frequencies? Would moving to a different FPGA bank resolve the issue (which I unfortunately cannot really do until I make this into a custom board and take it off the dev board).

    It's strange, and I would like to figure out what is going on, but in the mean time I suspect adding some capacitors next to the inputs of the ADV7513 on MCLK, LRCLK and SCLK should make it work as I want.

  • Hi,

    Please ensure your PCB layout is correct at HDMI Layout Guideline 

    However, if you are working on a new board, You will need to verify that the ADV7513 is connected correctly to the HDMI connector and that the PCB layout is correct.

    Kindly note, the exposed pad must be tied to ground.

    Make sure all power rails to chip have fat traces, almost planes if you can.

    All power supplies are well-regulated and clean, Especially PVDD and AVDD.

    This  AN-1270 (Rev. 0) ( application note shows a basic configuration in which a field programmable gate array (FPGA) is used as a signal source, producing sync timing and a video pattern, and the ADV7511/ ADV7511W/ADV7513 are configured to output a valid High Definition Multimedia Interface (HDMI®) or digital visual interface (DVI) stream
    For more information, please refer this application note: