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ADV7280 I2C error with voltage under 1,82V

Category: Hardware
Product Number: ADV7280BCPZ
Software Version: -


I have an ADV7280 connected to the host processor Nuvoton N32926 which shares 1,85V regulated power supply with the ADV.

Due to a more narrow voltage range specification of the new processor version, I had to modify the power supply voltage level, bringing the previous 1,85V to the new 1.79V.

This voltage rail applies to PVDD, DVDD and AVDD of ADV7280 (DVDDIO is at 3,3V). The regulator is a DCDC 1MHz 1,5A which can supply ADV current as requested in the datasheet and hardware guide.

At this new 1.79V voltage, ADV does not talk appropriately via I2C interface by blocking the SDA signal to a low level and showing "deal with nack" error in the processor console. This also affects communicating with other I2C devices.

To unlock the situation a reset signal must be asserted to ADV and SDA will be released, but at the new I2C writing, the error appears again frequently.

I monitored the voltage rail but I have not found fast voltage drops during the I2C initialization phase, just a steady reduction of 20mVdc during ADV startup due to copper rail resistance from the regulator to ADV supply pins.

However, I believe the voltage is far from the 1,71V indicated in the datasheet as the minimum request. If I revert the modification, the ADV works well again.

I found in a few samples that the voltage must not be under 1,81-1,82V to work properly, otherwise, the communication problem occurs.

Could someone help me to understand the problem? 



Best regards

  • Hi,

     As per specification, the I2C lines should work with 1.8V signals. They are 5V tolerant.

    The optimal power-up sequence for the ADV7280A is to first power up the 3.3 V DVDDIO supply, followed by the 1.8 V supplies: DVDD, PVDD, AVDD, and MVDD (for the ADV7280A-M)

    Connect any pull-up resistors connected to pins on the ADV7280A (such as the SCLK and SDATA pins) to 1.8 V instead of 3.3 V for more information please refer the POWER SUPPLY SEQUENCING in data sheet

    Generally, VDD_IO can be operated at either 1.8V or 3.3V. When operating at 3.3V,the voltage limits are between 2.97 V to 3.63 V and when operating at 1.8V the voltage limits are between 1.71V to 1.89V. This is how the datasheet specifies.

    When VDD_IO is set to 1.8 V, all the digital video inputs and control inputs, such as I2C, HS, and VS, should be 1.8V levels. Vdd_io and Vaa are nominally 3.3V rails while Vdd and PVdd are 1.8V rails.

    Note: ADV7282A can be powered from a single 1.8V supply.
    DVDDIO, DVDD, AVDD, PVDD can be powered simultaneously.
    During this event, the PWRDWN pin and the RESET pin must remain asserted (active low).
    After the 1.8V supply rails are fully asserted (up and stable), the PWRDWN pin can be deasserted (released high).
    After the PWRDWN pin is released high, wait 5ms and then deassert the RESET (release high).
    After the RESET pin is released, wait a further 5ms before initiating I2C communication with the ADV7282A.