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[ADV7480] MIPI output status

Category: Software

Hi,

I have some questions about the MIPI output of the ADV7480.

I asked about the MIPI output state in the start-up/power-down sequence

in the following session.

(MIPI output status)

Q1) When the following MIPI-TXA power down processing is executed, will the MIPI output be LP-11?

       I understand that the output does not go from HS to LP state immediately.

        CSI-TXA Map

         1) 94  31  82

         2) 94  1E  00

         3) 94  00  84

         4) 94  DA  00

         5) 94  C1  3B

Q2) In the following MIPI-TXA startup processing,

       I think that it will be in the LP state around the 12th step.

       Is the LP state in this case LP-11?   

        CSI-TXA Map

         1) 94  00  84

         2) 94  00  A4

         3) 94  DB  10

         4) 94  D6  07

         5) 94  C4  0A

         6) 94  71  33

         7) 94  72  11

         8) 94  F0  00

         9) 94  31  82

         10) 94  1E  40

         11) 94  DA  01

         12) 94  00  24

         13) 94  C1  2B

         14) 94  31  80

Best regards.

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  • Hi,

    Thank you for your reply.

    I have additional questions.

    Q1) After going into LP mode, will the clock lane go into LP mode as well as the data lane?

          Or will the clock continue to output?

    Q2) If the answer to Q1) is that the clock continues to output and does not enter the LP-11 state,

           I am thinking of setting the MIPI output to Hi-Z.

           Is it possible with register settings?

    Best regards.

  • Hi Tatsuya San,

        Please find the below comments,

         Q1) As per expert comment, the outputs will not immediately go into LP state from HS. The transmitter will finish out the current video line.

    Please note "CSITX_PWRDN bit will power up or down the Tx and this roughly equates to enabling or disabling the clock lane.

    Also even when we disable the Tx by using CSITX_PWRD bit, the outputs will not immediately go into LP state from HS. The transmitter will finish out the current video line" Since 'CSITX_PWRD' bit does not transfer directly over to controlling the LP or HS state on the MIPI outputs.

    Please refer here (+) (ADV7480)Can we control LP⇔HS mode using  CSITX_PWRDN bit ? - Q&A - Video - EngineerZone (analog.com)

       Q2) We don't find any registers for tristating(Hi-Z) the MIPI outputs, Could you please try with "DPHY_PWDN" register.

    Thanks,

    Poornima