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[ADV7441A]Output VSYNC behavior after video signal input.

Category: Hardware
Product Number: ADV7441A

Hi Team.

I'd like to ask you about Video Decoder IC, ADV7441A.
We are using the ADV7441A to decode RS-170A.

As described in the data sheet, Vsync locks at 2 fields after video signal input,
but vsync becomes low level for 1 field at the 8th field after locking.
I have only confirmed this with 1 sample, but when this event occurs,
it always occurs on the 8th field.
This event occurs every few times.
What is the mechanism by which this event occurs?
We have confirmed that the output clock is stable at the time this situation occurs.

The sequence is carried out in the following order
Reset release, register setting, video input.

The acquisition waveforms at that time are attached for reference.
Yellow: Video input (RS-170A)
Green: Video input start flag
Blue: Output Vsync
Red: Output clock (LLC)

Parents Reply
  • Poornima-san

    Our application sets the video input manually (SETADC_SW_MAN_EN=1)
    Therefore, I didn't know which setting to apply in the script I received.
    The pin assignment and specifications of the input video signal are as follows.

    *Video Specifications
    ADV Input : RS-170A compliant RGB color analog video(Sync on Green)
    Number of Pixels : Stripe 720px * 480px
    Display Color : RGB
    Gradation : 1024
    Scanning Format : Interlace
    Horizontal scanning period : 2 * fSC / 455(fSC=3.579545MHz +/-50ppm)
    Vertical scanning period : 2 * fH / 525

    *Pin Assignment

    The register is set by the following script.
    Are there any problems or missing settings?
    Target Address : 0x40(ALSB = Low)
    40 00 00
    40 03 11
    40 05 00
    40 06 0A
    40 87 AD
    40 88 AC
    40 1D 40
    40 6A 4F
    40 3C 5A
    40 47 0A
    40 67 01
    40 68 F2
    40 7B 04
    40 7D 03
    40 7E 03
    40 8F 00
    40 F3 07
    40 8A 10
    40 85 19
    40 C3 31
    40 C4 C2
    40 73 17
    40 74 25
    40 75 C9
    40 76 72
    40 6C 10
    40 6D 00
    40 6E 00
    40 6F 00
    40 70 00
    40 BF 16
    40 C0 00
    40 C1 00
    40 C2 00
    40 6C D4
    40 6D F4
    40 6E 4F
    40 6F 44
    40 70 F4
    40 0C 34
    40 31 1A
    40 32 81
    40 35 00
    40 36 7D
    40 37 A1
    40 E5 41
    40 E6 84
    40 E7 06

    Best Regards.


  • Hi Takuya San,

       Could you please do the below register configuration according to the reference script and let us know the result.

    ##CP 1080p##:1080p/60Hz RGB In 1X1 30Bit 444 RGB Out through DAC:

    42 03 0C ; Disable TOD
    42 05 01 ; Prim_Mode =001b COMP
    42 06 04 ; VID_STD=00100 (720x480)
    42 1D 40 ; Disable TRI_LLC
    42 37 00 ; Disable PCLK
    42 3C A8 ; SOG Sync level for atenuated sync, PLL Qpump to default
    42 47 0A ; Enable Automatic PLL_Qpump and VCO Range
    42 67 01 ; RGB Full Range Input Colour Space
    42 68 F2 ; Auto CSC , RGB Out
    42 7B 14 ; TURN OFF EAV & SAV CODES
    42 85 02 ; Autodetect Sync Source
    42 C3 31 ; Manual Muxing
    42 C4 F2 ; Manual Muxing
    42 BA A0 ; Enable HDMI and Analog in
    42 F4 15 ; Max Drive Strength
    54 00 FD ; power down encoder
    50 10 01 ; DAC channel enabled

    Also please note "Most of our video decoders can able to handle RS-170, Since it's basically an NTSC without color. You'll get NTSC timings out of it. ADV7441A, with Color Kill turned on-- RS170 should work".



  • Hi Poornima-san

    As a result of investigating multiple patterns based on the register setting values you provided, the event no longer occurs by setting DS_OUT to 0.
    From this result, can you deduce the mechanism of the phenomenon that was the problem this time?
    Setting DS_OUT to 0 makes LLC and VS out of sync, which is undesirable in our application.
    Is there any other way to avoid this?

    Best Regards.


  • Hi Takuya San,

            Please ensure, How H&V synchs from your source connected to the ADV7441A ? Also you will get asynchronous VS output if DS_OUT to '0' 

           DS_OUT bit then enables selection between a synchronous VS signal (synchronous to True Line Locked Clock) and an asynchronous version of the vertical synchronization. Depending on the application and the ultimate purpose of the timing signal, both of them can have distinct advantages.

        DS_OUT signal selects between the following signals:
           Asynchronous composite-style synchronization signal derived from either the digital HS and VS or the embedded synchronization (SOG). Macrovision impairments may be present.
           Sequence of generated horizontal synchronization pulses where Macrovision impairments,
    such as pseudo-synchronization pulses, have been removed.




  • Hi Poornima-san

    It uses the SOG pin as a sync source.

    This signal connects the analog input green signal through a 1nF capacitor. This connection is based on the circuit on the evaluation board.

    I understand that setting DS_OUT to 0 will generate VS_OUT synchronous to XTAL, and thus asynchronous to LLC.

    What we want to know is why LLC-synchronized VS_OUT rarely asserts low after Vsync lock.

    In our evaluation, when this event occurs, it always occurs in the 8th field after Vsync lock.

    This phenomenon seems very logical.

    If the mechanism of this event is clarified and this event always occurs only in the 8th field, countermeasures such as ignoring this event can be taken at that timing.

    From the evaluation results so far, it seems to be related to LLC, but when I checked the output of LLC, it seemed to stabilize at the specified frequency before this event occurred.

    In other words, I think that the signal input to SOG is sufficiently stable.


    Best Regards.


  • Hi,

      Its hard to find out what going wrong to make Vsync becomes low level in the 8th field after locking.

      If possible, Could you please check the same in our evaluation board and if this is reproducible in our evaluation board then we can check with part specialist about this.