I'd like to ask you about Video Decoder IC, ADV7441A.
We are using the ADV7441A to decode RS-170A.
As described in the data sheet, Vsync locks at 2 fields after video signal input,
but vsync becomes low level for 1 field at the 8th field after locking.
I have only confirmed this with 1 sample, but when this event occurs,
it always occurs on the 8th field.
This event occurs every few times.
What is the mechanism by which this event occurs?
We have confirmed that the output clock is stable at the time this situation occurs.
The sequence is carried out in the following order
Reset release, register setting, video input.
The acquisition waveforms at that time are attached for reference.
Yellow: Video input (RS-170A)
Green: Video input start flag
Blue: Output Vsync
Red: Output clock (LLC)