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ADV7280M Android 11 integration

Category: Software
Product Number: ADV7280M
Software Version: Android 11

Hi,

please have a look at the below schematics 

We are trying to connect a NTSC Analog camera to IMX8M Mini using ADV7280M

Please find the changes below 

From 73dc25ef52b6d4c0c3727a006d8160b9f739cdaf Mon Sep 17 00:00:00 2001
From: Tarun Kapadia <tarun.kapadia@ltts.com>
Date: Fri, 12 Aug 2022 13:46:52 +0530
Subject: [PATCH] [WIP] media: adv7180: Bring up for adv7280M

Signed-off-by: Tarun Kapadia <tarun.kapadia@ltts.com>
---
 arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi |  51 +++-
 arch/arm64/configs/imx_v8_android_defconfig   |   2 +
 drivers/media/i2c/adv7180.c                   | 343 +++++++++++++++++++++++---
 3 files changed, 350 insertions(+), 46 deletions(-)

diff --git a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
index 1dedfaa..15cab16 100755
--- a/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
+++ b/arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi
@@ -437,7 +437,7 @@
 
 &csi1_bridge {
 	fsl,mipi-mode;
-	status = "disabled";
+	status = "okay";
 	port {
 		csi1_ep: endpoint {
 			remote-endpoint = <&csi1_mipi_ep>;
@@ -650,6 +650,26 @@
 		};
 	};
 
+        adv7280m: adv7280@21 {
+                compatible = "adi,adv7280-m";
+                reg = <0x21>;
+                pinctrl-names = "default";
+                pinctrl-0 = <&pinctrl_csi_rst>;
+                reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;
+                irq-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>; 
+                interupt-parent = <&gpio1>;
+                interrupt = <6 GPIO_ACTIVE_LOW>;
+                adv,force-bt656-4 = <1>;
+                status = "okay";
+                port {
+                        adv7280m_out: endpoint {
+                               clock-lanes = <0>;
+                               data-lanes = <1>;
+                               remote-endpoint = <&mipi1_sensor_ep>;
+                        };
+                };
+        };
+
 	lvds_bridge: sn65dsi83@2c {
 		compatible = "ti,sn65dsi83";
 		reg = <0x2c>;
@@ -782,7 +802,6 @@
 	ov5640_mipi: ov5640_mipi@3c {
 		compatible = "ovti,ov5640_mipi";
 		reg = <0x3c>;
-		status = "disabled";
 		pinctrl-names = "default";
 		pinctrl-0 = <&pinctrl_csi_pwn>, <&pinctrl_csi_rst>;
 		clocks = <&clk IMX8MM_CLK_CLKO1>;
@@ -794,6 +813,7 @@
 		pwn-gpios = <&gpio1 7 GPIO_ACTIVE_HIGH>;
 		mclk = <24000000>;
 		mclk_source = <0>;
+		status = "disabled";
 		port {
 			ov5640_mipi1_ep: endpoint {
 				remote-endpoint = <&mipi1_sensor_ep>;
@@ -898,11 +918,11 @@
 &mipi_csi_1 {
 	#address-cells = <1>;
 	#size-cells = <0>;
-	status = "disabled";
+	status = "okay";
 	port {
 		mipi1_sensor_ep: endpoint@1 {
-			remote-endpoint = <&ov5640_mipi1_ep>;
-			data-lanes = <2>;
+			remote-endpoint = <&adv7280m_out>;
+			data-lanes = <1>;
 			csis-hs-settle = <13>;
 			csis-clk-settle = <2>;
 			csis-wclk;
@@ -1170,12 +1190,23 @@
 		>;
 	};
 
-	pinctrl_csi_rst: csi_rst_grp {
+	/*pinctrl_csi_rst: csi_rst_grp {
 		fsl,pins = <
 			MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6		0x19
 			MX8MM_IOMUXC_GPIO1_IO14_CCMSRCGPCMIX_CLKO1	0x59
 		>;
-	};
+	};*/
+
+        pinctrl_csi_rst: csi_rst_grp {
+                fsl,pins = <
+                       MX8MM_IOMUXC_GPIO1_IO06_GPIO1_IO6               0x116
+                       MX8MM_IOMUXC_GPIO1_IO14_GPIO1_IO14              0x116
+                       MX8MM_IOMUXC_ENET_RD2_GPIO1_IO28                0x19
+                       MX8MM_IOMUXC_ENET_TXC_GPIO1_IO23                0x19
+                       MX8MM_IOMUXC_SD2_CD_B_GPIO2_IO12                0x19
+                >;
+        };
+
 
 	pinctrl_ecspi1: ecspi1grp {
                 fsl,pins = <
@@ -1214,10 +1245,10 @@
 			MX8MM_IOMUXC_ENET_TD1_ENET1_RGMII_TD1		0x1f
 			MX8MM_IOMUXC_ENET_TD0_ENET1_RGMII_TD0		0x1f
 			MX8MM_IOMUXC_ENET_RD3_ENET1_RGMII_RD3		0x91
-			MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91
+			/*MX8MM_IOMUXC_ENET_RD2_ENET1_RGMII_RD2		0x91*/
 			MX8MM_IOMUXC_ENET_RD1_ENET1_RGMII_RD1		0x91
 			MX8MM_IOMUXC_ENET_RD0_ENET1_RGMII_RD0		0x91
-			MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f
+			/*MX8MM_IOMUXC_ENET_TXC_ENET1_RGMII_TXC		0x1f*/
 			MX8MM_IOMUXC_ENET_RXC_ENET1_RGMII_RXC		0x91
 			MX8MM_IOMUXC_ENET_RX_CTL_ENET1_RGMII_RX_CTL	0x91
 			MX8MM_IOMUXC_ENET_TX_CTL_ENET1_RGMII_TX_CTL	0x1f
@@ -1508,7 +1539,7 @@
 
 	pinctrl_usdhc2_gpio: usdhc2grpgpiogrp {
 		fsl,pins = <
-			MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 	0x41 	
+			/*MX8MM_IOMUXC_SD2_CD_B_USDHC2_CD_B 	0x41 	*/
 		>;
 	};
 
diff --git a/arch/arm64/configs/imx_v8_android_defconfig b/arch/arm64/configs/imx_v8_android_defconfig
index f1d9c04..5e75b53 100644
--- a/arch/arm64/configs/imx_v8_android_defconfig
+++ b/arch/arm64/configs/imx_v8_android_defconfig
@@ -1184,3 +1184,5 @@ CONFIG_SSB_DRIVER_PCICORE=y
 CONFIG_BCMA=y
 CONFIG_CORDIC=y
 CONFIG_IIO_ST_ACC33=y
+CONFIG_VIDEO_ADV7180=y
+
diff --git a/drivers/media/i2c/adv7180.c b/drivers/media/i2c/adv7180.c
index 4498d14..9de0080 100644
--- a/drivers/media/i2c/adv7180.c
+++ b/drivers/media/i2c/adv7180.c
@@ -66,6 +66,9 @@
 #define ADV7180_HUE_DEF		0
 #define ADV7180_HUE_MAX		128
 
+#define ADV7180_REG_DEF_VALUE_Y	0x000c
+#define ADV7180_DEF_VAL_EN		0x1
+#define ADV7180_DEF_VAL_AUTO_EN	0x2
 #define ADV7180_REG_CTRL		0x000e
 #define ADV7180_CTRL_IRQ_SPACE		0x20
 
@@ -94,6 +97,7 @@
 #define ADV7180_REG_SHAP_FILTER_CTL_1	0x0017
 #define ADV7180_REG_CTRL_2		0x001d
 #define ADV7180_REG_VSYNC_FIELD_CTL_1	0x0031
+#define ADV7180_VSYNC_FIELD_CTL_1_NEWAV 0x12
 #define ADV7180_REG_MANUAL_WIN_CTL_1	0x003d
 #define ADV7180_REG_MANUAL_WIN_CTL_2	0x003e
 #define ADV7180_REG_MANUAL_WIN_CTL_3	0x003f
@@ -205,6 +209,7 @@ struct adv7180_state {
 	struct mutex		mutex; /* mutual excl. when accessing chip */
 	int			irq;
 	struct gpio_desc	*pwdn_gpio;
+	struct gpio_desc	*rst_gpio;
 	v4l2_std_id		curr_norm;
 	bool			powered;
 	bool			streaming;
@@ -216,6 +221,7 @@ struct adv7180_state {
 	struct i2c_client	*vpp_client;
 	const struct adv7180_chip_info *chip_info;
 	enum v4l2_field		field;
+	bool			force_bt656_4;
 };
 #define to_adv7180_sd(_ctrl) (&container_of(_ctrl->handler,		\
 					    struct adv7180_state,	\
@@ -223,6 +229,7 @@ struct adv7180_state {
 
 static int adv7180_select_page(struct adv7180_state *state, unsigned int page)
 {
+	pr_err("%s: Enter\n",__func__);
 	if (state->register_page != page) {
 		i2c_smbus_write_byte_data(state->client, ADV7180_REG_CTRL,
 			page);
@@ -235,6 +242,7 @@ static int adv7180_select_page(struct adv7180_state *state, unsigned int page)
 static int adv7180_write(struct adv7180_state *state, unsigned int reg,
 	unsigned int value)
 {
+        pr_err("%s: Enter reg = 0x%x value = 0x%x \n",__func__, reg, value);
 	lockdep_assert_held(&state->mutex);
 	adv7180_select_page(state, reg >> 8);
 	return i2c_smbus_write_byte_data(state->client, reg & 0xff, value);
@@ -242,6 +250,7 @@ static int adv7180_write(struct adv7180_state *state, unsigned int reg,
 
 static int adv7180_read(struct adv7180_state *state, unsigned int reg)
 {
+        pr_err("%s: Enter reg = %x\n",__func__, reg);
 	lockdep_assert_held(&state->mutex);
 	adv7180_select_page(state, reg >> 8);
 	return i2c_smbus_read_byte_data(state->client, reg & 0xff);
@@ -250,18 +259,21 @@ static int adv7180_read(struct adv7180_state *state, unsigned int reg)
 static int adv7180_csi_write(struct adv7180_state *state, unsigned int reg,
 	unsigned int value)
 {
+        pr_err("%s: Enter reg = 0x%x value = 0x%x\n",__func__, reg, value);
 	return i2c_smbus_write_byte_data(state->csi_client, reg, value);
 }
 
 static int adv7180_set_video_standard(struct adv7180_state *state,
 	unsigned int std)
 {
+        pr_err("%s: Enter\n",__func__);
 	return state->chip_info->set_std(state, std);
 }
 
 static int adv7180_vpp_write(struct adv7180_state *state, unsigned int reg,
 	unsigned int value)
 {
+        pr_err("%s: Enter reg = 0x%x value = 0x%x\n",__func__, reg, value);
 	return i2c_smbus_write_byte_data(state->vpp_client, reg, value);
 }
 
@@ -295,6 +307,8 @@ static v4l2_std_id adv7180_std_to_v4l2(u8 status1)
 
 static int v4l2_std_to_adv7180(v4l2_std_id std)
 {
+        pr_err("%s: Enter\n",__func__);
+
 	if (std == V4L2_STD_PAL_60)
 		return ADV7180_STD_PAL60;
 	if (std == V4L2_STD_NTSC_443)
@@ -318,6 +332,8 @@ static int v4l2_std_to_adv7180(v4l2_std_id std)
 
 static u32 adv7180_status_to_v4l2(u8 status1)
 {
+        pr_err("%s: Enter\n",__func__);
+
 	if (!(status1 & ADV7180_STATUS1_IN_LOCK))
 		return V4L2_IN_ST_NO_SIGNAL;
 
@@ -328,6 +344,7 @@ static int __adv7180_status(struct adv7180_state *state, u32 *status,
 			    v4l2_std_id *std)
 {
 	int status1 = adv7180_read(state, ADV7180_REG_STATUS1);
+        pr_err("%s: Enter\n",__func__);
 
 	if (status1 < 0)
 		return status1;
@@ -342,17 +359,20 @@ static int __adv7180_status(struct adv7180_state *state, u32 *status,
 
 static inline struct adv7180_state *to_state(struct v4l2_subdev *sd)
 {
+        pr_err("%s: Enter\n",__func__);
 	return container_of(sd, struct adv7180_state, sd);
 }
 
 static int adv7180_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
 {
+        pr_err("%s: Enter\n",__func__);
 	struct adv7180_state *state = to_state(sd);
 	int err = mutex_lock_interruptible(&state->mutex);
 	if (err)
 		return err;
 
 	if (state->streaming) {
+		pr_err("%s: -EBUSY");
 		err = -EBUSY;
 		goto unlock;
 	}
@@ -379,6 +399,7 @@ static int adv7180_querystd(struct v4l2_subdev *sd, v4l2_std_id *std)
 static int adv7180_s_routing(struct v4l2_subdev *sd, u32 input,
 			     u32 output, u32 config)
 {
+        pr_err("%s: Enter\n",__func__);
 	struct adv7180_state *state = to_state(sd);
 	int ret = mutex_lock_interruptible(&state->mutex);
 
@@ -401,6 +422,7 @@ static int adv7180_s_routing(struct v4l2_subdev *sd, u32 input,
 
 static int adv7180_g_input_status(struct v4l2_subdev *sd, u32 *status)
 {
+        pr_err("%s: Enter\n",__func__);
 	struct adv7180_state *state = to_state(sd);
 	int ret = mutex_lock_interruptible(&state->mutex);
 	if (ret)
@@ -414,6 +436,7 @@ static int adv7180_g_input_status(struct v4l2_subdev *sd, u32 *status)
 static int adv7180_program_std(struct adv7180_state *state)
 {
 	int ret;
+        pr_err("%s: Enter\n",__func__);
 
 	ret = v4l2_std_to_adv7180(state->curr_norm);
 	if (ret < 0)
@@ -429,6 +452,7 @@ static int adv7180_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
 {
 	struct adv7180_state *state = to_state(sd);
 	int ret = mutex_lock_interruptible(&state->mutex);
+        pr_err("%s: Enter\n",__func__);
 
 	if (ret)
 		return ret;
@@ -449,6 +473,7 @@ static int adv7180_s_std(struct v4l2_subdev *sd, v4l2_std_id std)
 static int adv7180_g_std(struct v4l2_subdev *sd, v4l2_std_id *norm)
 {
 	struct adv7180_state *state = to_state(sd);
+        pr_err("%s: Enter\n",__func__);
 
 	*norm = state->curr_norm;
 
@@ -459,6 +484,7 @@ static int adv7180_g_frame_interval(struct v4l2_subdev *sd,
 				    struct v4l2_subdev_frame_interval *fi)
 {
 	struct adv7180_state *state = to_state(sd);
+        pr_err("%s: Enter\n",__func__);
 
 	if (state->curr_norm & V4L2_STD_525_60) {
 		fi->interval.numerator = 1001;
@@ -473,6 +499,8 @@ static int adv7180_g_frame_interval(struct v4l2_subdev *sd,
 
 static void adv7180_set_power_pin(struct adv7180_state *state, bool on)
 {
+        pr_err("%s: Enter\n",__func__);
+
 	if (!state->pwdn_gpio)
 		return;
 
@@ -484,10 +512,26 @@ static void adv7180_set_power_pin(struct adv7180_state *state, bool on)
 	}
 }
 
+static void adv7180_set_reset_pin(struct adv7180_state *state, bool on)
+{
+        pr_err("%s: Enter on = %d \n",__func__, on);
+
+	if (!state->rst_gpio)
+		return;
+
+	if (on) {
+		gpiod_set_value_cansleep(state->rst_gpio, 1);
+	} else {
+		gpiod_set_value_cansleep(state->rst_gpio, 0);
+		usleep_range(5000, 10000);
+	}
+}
+
 static int adv7180_set_power(struct adv7180_state *state, bool on)
 {
 	u8 val;
 	int ret;
+        pr_err("%s: Enter\n",__func__);
 
 	if (on)
 		val = ADV7180_PWR_MAN_ON;
@@ -520,6 +564,7 @@ static int adv7180_s_power(struct v4l2_subdev *sd, int on)
 {
 	struct adv7180_state *state = to_state(sd);
 	int ret;
+        pr_err("%s: Enter\n",__func__);
 
 	ret = mutex_lock_interruptible(&state->mutex);
 	if (ret)
@@ -533,6 +578,41 @@ static int adv7180_s_power(struct v4l2_subdev *sd, int on)
 	return ret;
 }
 
+static const char * const test_pattern_menu[] = {
+	"Single color",
+	"Color bars",
+	"Luma ramp",
+	"Boundary box",
+	"Disable",
+};
+
+static int adv7180_test_pattern(struct adv7180_state *state, int value)
+{
+	unsigned int reg = 0;
+
+        pr_err("%s: Enter\n",__func__);
+	/* Map menu value into register value */
+	if (value < 3)
+		reg = value;
+	if (value == 3)
+		reg = 5;
+
+	adv7180_write(state, ADV7180_REG_ANALOG_CLAMP_CTL, reg);
+
+	if (value == ARRAY_SIZE(test_pattern_menu) - 1) {
+		reg = adv7180_read(state, ADV7180_REG_DEF_VALUE_Y);
+		reg &= ~ADV7180_DEF_VAL_EN;
+		adv7180_write(state, ADV7180_REG_DEF_VALUE_Y, reg);
+		return 0;
+	}
+
+	reg = adv7180_read(state, ADV7180_REG_DEF_VALUE_Y);
+	reg |= ADV7180_DEF_VAL_EN | ADV7180_DEF_VAL_AUTO_EN;
+	adv7180_write(state, ADV7180_REG_DEF_VALUE_Y, reg);
+
+	return 0;
+}
+
 static int adv7180_s_ctrl(struct v4l2_ctrl *ctrl)
 {
 	struct v4l2_subdev *sd = to_adv7180_sd(ctrl);
@@ -540,6 +620,7 @@ static int adv7180_s_ctrl(struct v4l2_ctrl *ctrl)
 	int ret = mutex_lock_interruptible(&state->mutex);
 	int val;
 
+        pr_err("%s: Enter\n",__func__);
 	if (ret)
 		return ret;
 	val = ctrl->val;
@@ -576,6 +657,9 @@ static int adv7180_s_ctrl(struct v4l2_ctrl *ctrl)
 			adv7180_write(state, ADV7180_REG_FLCONTROL, 0x00);
 		}
 		break;
+	case V4L2_CID_TEST_PATTERN:
+		ret = adv7180_test_pattern(state, val);
+		break;
 	default:
 		ret = -EINVAL;
 	}
@@ -616,6 +700,12 @@ static int adv7180_init_controls(struct adv7180_state *state)
 			  ADV7180_HUE_MAX, 1, ADV7180_HUE_DEF);
 	v4l2_ctrl_new_custom(&state->ctrl_hdl, &adv7180_ctrl_fast_switch, NULL);
 
+	v4l2_ctrl_new_std_menu_items(&state->ctrl_hdl, &adv7180_ctrl_ops,
+				      V4L2_CID_TEST_PATTERN,
+				      ARRAY_SIZE(test_pattern_menu) - 1,
+				      0, ARRAY_SIZE(test_pattern_menu) - 1,
+				      test_pattern_menu);
+
 	state->sd.ctrl_handler = &state->ctrl_hdl;
 	if (state->ctrl_hdl.error) {
 		int err = state->ctrl_hdl.error;
@@ -633,14 +723,16 @@ static void adv7180_exit_controls(struct adv7180_state *state)
 }
 
 static int adv7180_enum_mbus_code(struct v4l2_subdev *sd,
-				  struct v4l2_subdev_pad_config *cfg,
+				  struct v4l2_subdev_state *sd_state,
 				  struct v4l2_subdev_mbus_code_enum *code)
 {
+        pr_err("%s: Enter\n",__func__);
+
 	if (code->index != 0)
 		return -EINVAL;
 
-	code->code = MEDIA_BUS_FMT_UYVY8_2X8;
-
+	//code->code = MEDIA_BUS_FMT_UYVY8_2X8;
+        code->code = MEDIA_BUS_FMT_YUYV8_2X8;
 	return 0;
 }
 
@@ -648,25 +740,34 @@ static int adv7180_mbus_fmt(struct v4l2_subdev *sd,
 			    struct v4l2_mbus_framefmt *fmt)
 {
 	struct adv7180_state *state = to_state(sd);
+        pr_err("%s: Enter\n",__func__);
 
-	fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
+	//fmt->code = MEDIA_BUS_FMT_UYVY8_2X8;
+        fmt->code = MEDIA_BUS_FMT_YUYV8_2X8;
 	fmt->colorspace = V4L2_COLORSPACE_SMPTE170M;
 	fmt->width = 720;
+	/*fmt->height = 480;*/
 	fmt->height = state->curr_norm & V4L2_STD_525_60 ? 480 : 576;
 
-	if (state->field == V4L2_FIELD_ALTERNATE)
+	if (state->field == V4L2_FIELD_ALTERNATE) {
+		pr_err("%s: V4L2_FIELD_ALTERNATE height = 240", __func__);
 		fmt->height /= 2;
-
+	}
 	return 0;
 }
 
 static int adv7180_set_field_mode(struct adv7180_state *state)
 {
-	if (!(state->chip_info->flags & ADV7180_FLAG_I2P))
+        pr_err("%s: Enter\n",__func__);
+
+	if (!(state->chip_info->flags & ADV7180_FLAG_I2P)) {
+		pr_err("%s: !flags & I2P", __func__);
 		return 0;
+	}
 
 	if (state->field == V4L2_FIELD_NONE) {
 		if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
+			pr_err("%s: MIPI_CSI2 && V4L2_FIELD_NONE",__func__);
 			adv7180_csi_write(state, 0x01, 0x20);
 			adv7180_csi_write(state, 0x02, 0x28);
 			adv7180_csi_write(state, 0x03, 0x38);
@@ -679,6 +780,7 @@ static int adv7180_set_field_mode(struct adv7180_state *state)
 		adv7180_vpp_write(state, 0xa3, 0x00);
 		adv7180_vpp_write(state, 0x5b, 0x00);
 		adv7180_vpp_write(state, 0x55, 0x80);
+		pr_err("%s: I2P Core Enabled",__func__);
 	} else {
 		if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
 			adv7180_csi_write(state, 0x01, 0x18);
@@ -699,15 +801,21 @@ static int adv7180_set_field_mode(struct adv7180_state *state)
 }
 
 static int adv7180_get_pad_format(struct v4l2_subdev *sd,
-				  struct v4l2_subdev_pad_config *cfg,
+				  struct v4l2_subdev_state *sd_state,
 				  struct v4l2_subdev_format *format)
 {
+
+        pr_err("%s: Enter\n",__func__);
 	struct adv7180_state *state = to_state(sd);
 
 	if (format->which == V4L2_SUBDEV_FORMAT_TRY) {
-		format->format = *v4l2_subdev_get_try_format(sd, cfg, 0);
+		format->format = *v4l2_subdev_get_try_format(sd, sd_state, 0);
 	} else {
 		adv7180_mbus_fmt(sd, &format->format);
+
+		pr_err("%s: format->format.field = %d state->field = %d",
+			__func__,format->format.field, state->field);
+
 		format->format.field = state->field;
 	}
 
@@ -715,62 +823,70 @@ static int adv7180_get_pad_format(struct v4l2_subdev *sd,
 }
 
 static int adv7180_set_pad_format(struct v4l2_subdev *sd,
-				  struct v4l2_subdev_pad_config *cfg,
+				  struct v4l2_subdev_state *sd_state,
 				  struct v4l2_subdev_format *format)
 {
 	struct adv7180_state *state = to_state(sd);
 	struct v4l2_mbus_framefmt *framefmt;
 	int ret;
-
+        pr_err("%s: Enter format->format.field = %d\n",__func__, format->format.field);
 	switch (format->format.field) {
 	case V4L2_FIELD_NONE:
 		if (state->chip_info->flags & ADV7180_FLAG_I2P)
 			break;
 		fallthrough;
 	default:
-		format->format.field = V4L2_FIELD_ALTERNATE;
+		pr_err("%s: V4L2_FIELD_NONE fallthrough set",__func__);
+		format->format.field = V4L2_FIELD_NONE;
 		break;
 	}
+	pr_err("%s: Final format->format.field = %d\n",__func__, format->format.field);
 
 	ret = adv7180_mbus_fmt(sd,  &format->format);
 
 	if (format->which == V4L2_SUBDEV_FORMAT_ACTIVE) {
+		pr_err("%s: V4L2_SUBDEV_FORMAT_ACTIVE", __func__);
 		if (state->field != format->format.field) {
+	                pr_err("%s: state->field = %d != format->format.field = %d", __func__, state->field, format->format.field);
 			state->field = format->format.field;
+                        pr_err("%s: format->format.field = %d", __func__, format->format.field);
 			adv7180_set_power(state, false);
 			adv7180_set_field_mode(state);
 			adv7180_set_power(state, true);
 		}
 	} else {
-		framefmt = v4l2_subdev_get_try_format(sd, cfg, 0);
+		framefmt = v4l2_subdev_get_try_format(sd, sd_state, 0);
 		*framefmt = format->format;
+		pr_err("%s: v4l2_subdev_get_try_format format->format.field = %d", __func__, format->format.field);
 	}
 
 	return ret;
 }
 
 static int adv7180_init_cfg(struct v4l2_subdev *sd,
-			    struct v4l2_subdev_pad_config *cfg)
+			    struct v4l2_subdev_state *sd_state)
 {
+        pr_err("%s: Enter\n",__func__);
 	struct v4l2_subdev_format fmt = {
-		.which = cfg ? V4L2_SUBDEV_FORMAT_TRY
-			: V4L2_SUBDEV_FORMAT_ACTIVE,
+		.which = sd_state ? V4L2_SUBDEV_FORMAT_TRY
+		: V4L2_SUBDEV_FORMAT_ACTIVE,
 	};
-
-	return adv7180_set_pad_format(sd, cfg, &fmt);
+	return adv7180_set_pad_format(sd, sd_state, &fmt);
 }
 
 static int adv7180_get_mbus_config(struct v4l2_subdev *sd,
 				   unsigned int pad,
 				   struct v4l2_mbus_config *cfg)
 {
+        pr_err("%s: Enter\n",__func__);
 	struct adv7180_state *state = to_state(sd);
 
 	if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
 		cfg->type = V4L2_MBUS_CSI2_DPHY;
 		cfg->flags = V4L2_MBUS_CSI2_1_LANE |
-				V4L2_MBUS_CSI2_CHANNEL_0 |
-				V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
+			 	V4L2_MBUS_CSI2_CHANNEL_0 |
+ 				V4L2_MBUS_CSI2_CONTINUOUS_CLOCK;
+		pr_err("%s: V4L2_MBUS_CSI2_CONTINUOUS_CLOCK",__func__);
 	} else {
 		/*
 		 * The ADV7180 sensor supports BT.601/656 output modes.
@@ -779,6 +895,7 @@ static int adv7180_get_mbus_config(struct v4l2_subdev *sd,
 		cfg->flags = V4L2_MBUS_MASTER | V4L2_MBUS_PCLK_SAMPLE_RISING |
 				 V4L2_MBUS_DATA_ACTIVE_HIGH;
 		cfg->type = V4L2_MBUS_BT656;
+		pr_err("%s: BT656",__func__);
 	}
 
 	return 0;
@@ -786,6 +903,8 @@ static int adv7180_get_mbus_config(struct v4l2_subdev *sd,
 
 static int adv7180_get_skip_frames(struct v4l2_subdev *sd, u32 *frames)
 {
+
+        pr_err("%s: Enter\n",__func__);
 	*frames = ADV7180_NUM_OF_SKIP_FRAMES;
 
 	return 0;
@@ -795,6 +914,7 @@ static int adv7180_g_pixelaspect(struct v4l2_subdev *sd, struct v4l2_fract *aspe
 {
 	struct adv7180_state *state = to_state(sd);
 
+        pr_err("%s: Enter\n",__func__);
 	if (state->curr_norm & V4L2_STD_525_60) {
 		aspect->numerator = 11;
 		aspect->denominator = 10;
@@ -808,6 +928,7 @@ static int adv7180_g_pixelaspect(struct v4l2_subdev *sd, struct v4l2_fract *aspe
 
 static int adv7180_g_tvnorms(struct v4l2_subdev *sd, v4l2_std_id *norm)
 {
+        pr_err("%s: Enter\n",__func__);
 	*norm = V4L2_STD_ALL;
 	return 0;
 }
@@ -817,16 +938,20 @@ static int adv7180_s_stream(struct v4l2_subdev *sd, int enable)
 	struct adv7180_state *state = to_state(sd);
 	int ret;
 
+        pr_err("%s: Enter\n",__func__);
 	/* It's always safe to stop streaming, no need to take the lock */
 	if (!enable) {
+		pr_err("%s: !enable",__func__);
 		state->streaming = enable;
 		return 0;
 	}
 
 	/* Must wait until querystd released the lock */
 	ret = mutex_lock_interruptible(&state->mutex);
-	if (ret)
+	if (ret) {
+		pr_err("%s: ret = %d",__func__,ret);
 		return ret;
+	}
 	state->streaming = enable;
 	mutex_unlock(&state->mutex);
 	return 0;
@@ -836,6 +961,7 @@ static int adv7180_subscribe_event(struct v4l2_subdev *sd,
 				   struct v4l2_fh *fh,
 				   struct v4l2_event_subscription *sub)
 {
+        pr_err("%s: Enter\n",__func__);
 	switch (sub->type) {
 	case V4L2_EVENT_SOURCE_CHANGE:
 		return v4l2_src_change_event_subdev_subscribe(sd, fh, sub);
@@ -846,6 +972,78 @@ static int adv7180_subscribe_event(struct v4l2_subdev *sd,
 	}
 }
 
+static int adv7180_enum_frame_size(struct v4l2_subdev *sd,
+                struct v4l2_subdev_pad_config *cfg,
+                struct v4l2_subdev_frame_size_enum *fse)
+{
+        pr_err("%s : Enter\n",__func__);
+
+        if (fse->index >= 1)
+                return -EINVAL;
+
+        fse->min_width = 720;
+        fse->min_height  = 480;
+        fse->max_width = 720;
+        fse->max_height  = 480;
+        //fse->code = MEDIA_BUS_FMT_UYVY8_2X8;
+	fse->code = MEDIA_BUS_FMT_YUYV8_2X8;
+        return 0;       
+}
+
+static int adv7180_enum_frame_interval(struct v4l2_subdev *sd,
+                struct v4l2_subdev_pad_config *cfg,
+                struct v4l2_subdev_frame_interval_enum *fie)
+{
+        pr_err("%s : Enter\n",__func__);
+
+        if (fie->index >= 1)
+                return -EINVAL;
+
+        fie->interval.numerator = 1;
+
+        int count = 0;
+	int i = 0;
+	int j = 0; 
+	
+        for (i = 0; i < 1; i++) {
+                for (j = 0; j < 1; j++) {
+                        if (fie->width  == 720 &&
+                            fie->height == 480)
+                                count++;
+
+                        if (fie->index == (count - 1)) {
+                                fie->interval.denominator = 30;
+                                return 0;
+                        }
+                }
+        }
+
+        return -EINVAL;
+
+}
+
+static int adv7180_s_parm(struct v4l2_subdev *sd, struct v4l2_streamparm *a)
+{
+	pr_err("%s: Enter\n", __func__);
+        switch (a->type) {
+        /* These are all the possible cases. */
+        case V4L2_BUF_TYPE_VIDEO_CAPTURE:
+        case V4L2_BUF_TYPE_VIDEO_OUTPUT:
+        case V4L2_BUF_TYPE_VIDEO_OVERLAY:
+        case V4L2_BUF_TYPE_VBI_CAPTURE:
+        case V4L2_BUF_TYPE_VBI_OUTPUT:
+        case V4L2_BUF_TYPE_SLICED_VBI_CAPTURE:
+        case V4L2_BUF_TYPE_SLICED_VBI_OUTPUT:
+                break;
+
+        default:
+                pr_err("   type is unknown - %d\n", a->type);
+                break;
+        }
+
+        return 0;
+}
+
 static const struct v4l2_subdev_video_ops adv7180_video_ops = {
 	.s_std = adv7180_s_std,
 	.g_std = adv7180_g_std,
@@ -856,6 +1054,8 @@ static int adv7180_subscribe_event(struct v4l2_subdev *sd,
 	.g_pixelaspect = adv7180_g_pixelaspect,
 	.g_tvnorms = adv7180_g_tvnorms,
 	.s_stream = adv7180_s_stream,
+	.s_parm = adv7180_s_parm,
+
 };
 
 static const struct v4l2_subdev_core_ops adv7180_core_ops = {
@@ -870,6 +1070,9 @@ static int adv7180_subscribe_event(struct v4l2_subdev *sd,
 	.set_fmt = adv7180_set_pad_format,
 	.get_fmt = adv7180_get_pad_format,
 	.get_mbus_config = adv7180_get_mbus_config,
+	.enum_frame_size = adv7180_enum_frame_size,
+	.enum_frame_interval = adv7180_enum_frame_interval,
+
 };
 
 static const struct v4l2_subdev_sensor_ops adv7180_sensor_ops = {
@@ -887,6 +1090,7 @@ static irqreturn_t adv7180_irq(int irq, void *devid)
 {
 	struct adv7180_state *state = devid;
 	u8 isr3;
+        pr_err("%s: Enter\n",__func__);
 
 	mutex_lock(&state->mutex);
 	isr3 = adv7180_read(state, ADV7180_REG_ISR3);
@@ -910,6 +1114,8 @@ static int adv7180_init(struct adv7180_state *state)
 {
 	int ret;
 
+        pr_err("%s: Enter\n",__func__);
+
 	/* ITU-R BT.656-4 compatible */
 	ret = adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
 			ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS);
@@ -923,6 +1129,8 @@ static int adv7180_init(struct adv7180_state *state)
 
 static int adv7180_set_std(struct adv7180_state *state, unsigned int std)
 {
+
+        pr_err("%s: Enter\n",__func__);
 	return adv7180_write(state, ADV7180_REG_INPUT_CONTROL,
 		(std << 4) | state->input);
 }
@@ -931,6 +1139,7 @@ static int adv7180_select_input(struct adv7180_state *state, unsigned int input)
 {
 	int ret;
 
+        pr_err("%s: Enter\n",__func__);
 	ret = adv7180_read(state, ADV7180_REG_INPUT_CONTROL);
 	if (ret < 0)
 		return ret;
@@ -942,13 +1151,22 @@ static int adv7180_select_input(struct adv7180_state *state, unsigned int input)
 
 static int adv7182_init(struct adv7180_state *state)
 {
-	if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2)
+        pr_err("%s: Enter\n",__func__);
+	pr_err("%s: flags = %d, ADV7180_I2P = %x", __func__, state->chip_info->flags,ADV7180_FLAG_I2P);
+
+	if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
+                pr_err("%s: VPP Slave Addr flags = %d, ADV7180_FLAG_MIPI_CSI2 = %x",
+			 __func__, state->chip_info->flags,ADV7180_FLAG_MIPI_CSI2);
 		adv7180_write(state, ADV7180_REG_CSI_SLAVE_ADDR,
 			ADV7180_DEFAULT_CSI_I2C_ADDR << 1);
+	}
 
-	if (state->chip_info->flags & ADV7180_FLAG_I2P)
+	if (state->chip_info->flags & ADV7180_FLAG_I2P) {
+	        pr_err("%s: VPP Slave Addr flags = %d, ADV7180_I2P = %x",
+		 __func__, state->chip_info->flags,ADV7180_FLAG_I2P);
 		adv7180_write(state, ADV7180_REG_VPP_SLAVE_ADDR,
 			ADV7180_DEFAULT_VPP_I2C_ADDR << 1);
+	}
 
 	if (state->chip_info->flags & ADV7180_FLAG_V2) {
 		/* ADI recommended writes for improved video quality */
@@ -963,10 +1181,27 @@ static int adv7182_init(struct adv7180_state *state)
 		adv7180_write(state, ADV7180_REG_EXTENDED_OUTPUT_CONTROL, 0x57);
 		adv7180_write(state, ADV7180_REG_CTRL_2, 0xc0);
 	} else {
-		if (state->chip_info->flags & ADV7180_FLAG_V2)
-			adv7180_write(state,
-				      ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
-				      0x17);
+		if (state->chip_info->flags & ADV7180_FLAG_V2) {
+			if (state->force_bt656_4) {
+				/* ITU-R BT.656-4 compatible */
+				adv7180_write(state,
+					      ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
+					      ADV7180_EXTENDED_OUTPUT_CONTROL_NTSCDIS);
+				pr_err("%s: bt656_4 set",__func__);
+				/* Manually set NEWAVMODE */
+				adv7180_write(state,
+					      ADV7180_REG_VSYNC_FIELD_CTL_1,
+					      ADV7180_VSYNC_FIELD_CTL_1_NEWAV);
+				/* Manually set V bit end position in NTSC mode */
+				adv7180_write(state,
+					      ADV7180_REG_NTSC_V_BIT_END,
+					      ADV7180_NTSC_V_BIT_END_MANUAL_NVEND);
+			} else {
+				adv7180_write(state,
+					      ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
+					      0x17);
+			}
+		}
 		else
 			adv7180_write(state,
 				      ADV7180_REG_EXTENDED_OUTPUT_CONTROL,
@@ -982,6 +1217,7 @@ static int adv7182_init(struct adv7180_state *state)
 
 static int adv7182_set_std(struct adv7180_state *state, unsigned int std)
 {
+        pr_err("%s: Enter\n",__func__);
 	return adv7180_write(state, ADV7182_REG_INPUT_VIDSEL, std << 4);
 }
 
@@ -994,6 +1230,7 @@ enum adv7182_input_type {
 
 static enum adv7182_input_type adv7182_get_input_type(unsigned int input)
 {
+        pr_err("%s: Enter input = %u \n",__func__, input);
 	switch (input) {
 	case ADV7182_INPUT_CVBS_AIN1:
 	case ADV7182_INPUT_CVBS_AIN2:
@@ -1044,6 +1281,8 @@ static int adv7182_select_input(struct adv7180_state *state, unsigned int input)
 	unsigned int i;
 	int ret;
 
+        pr_err("%s: Enter input = %u\n",__func__, input);
+
 	ret = adv7180_write(state, ADV7180_REG_INPUT_CONTROL, input);
 	if (ret)
 		return ret;
@@ -1054,6 +1293,8 @@ static int adv7182_select_input(struct adv7180_state *state, unsigned int input)
 
 	input_type = adv7182_get_input_type(input);
 
+        pr_err("%s: input_type = %d\n",__func__, input_type);
+
 	switch (input_type) {
 	case ADV7182_INPUT_TYPE_CVBS:
 	case ADV7182_INPUT_TYPE_DIFF_CVBS:
@@ -1074,13 +1315,15 @@ static int adv7182_select_input(struct adv7180_state *state, unsigned int input)
 		adv7180_write(state, ADV7180_REG_CVBS_TRIM + i, lbias[i]);
 
 	if (input_type == ADV7182_INPUT_TYPE_DIFF_CVBS) {
-		/* ADI required writes to make differential CVBS work */
+	        pr_err("%s: ADV7182_INPUT_TYPE_DIFF_CVBS\n",__func__);
+		/* ADI_ requirer writes to make differential CVBS work */
 		adv7180_write(state, ADV7180_REG_RES_CIR, 0xa8);
 		adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0x90);
 		adv7180_write(state, ADV7180_REG_DIFF_MODE, 0xb0);
 		adv7180_write(state, ADV7180_REG_AGC_ADJ1, 0x08);
 		adv7180_write(state, ADV7180_REG_AGC_ADJ2, 0xa0);
 	} else {
+	        pr_err("%s: NOT ADV7182_INPUT_TYPE_DIFF_CVBS\n",__func__);
 		adv7180_write(state, ADV7180_REG_RES_CIR, 0xf0);
 		adv7180_write(state, ADV7180_REG_CLAMP_ADJ, 0xd0);
 		adv7180_write(state, ADV7180_REG_DIFF_MODE, 0x10);
@@ -1261,8 +1504,10 @@ static int init_device(struct adv7180_state *state)
 	int ret;
 
 	mutex_lock(&state->mutex);
+        pr_err("%s: Enter\n",__func__);
 
 	adv7180_set_power_pin(state, true);
+	adv7180_set_reset_pin(state, false);
 
 	adv7180_write(state, ADV7180_REG_PWR_MAN, ADV7180_PWR_MAN_RES);
 	usleep_range(5000, 10000);
@@ -1314,10 +1559,12 @@ static int init_device(struct adv7180_state *state)
 static int adv7180_probe(struct i2c_client *client,
 			 const struct i2c_device_id *id)
 {
+	struct device_node *np = client->dev.of_node;
 	struct adv7180_state *state;
 	struct v4l2_subdev *sd;
 	int ret;
 
+        pr_err("%s: Enter\n",__func__);
 	/* Check if the adapter supports the needed features */
 	if (!i2c_check_functionality(client->adapter, I2C_FUNC_SMBUS_BYTE_DATA))
 		return -EIO;
@@ -1327,7 +1574,7 @@ static int adv7180_probe(struct i2c_client *client,
 		return -ENOMEM;
 
 	state->client = client;
-	state->field = V4L2_FIELD_ALTERNATE;
+	state->field = V4L2_FIELD_NONE;
 	state->chip_info = (struct adv7180_chip_info *)id->driver_data;
 
 	state->pwdn_gpio = devm_gpiod_get_optional(&client->dev, "powerdown",
@@ -1338,13 +1585,26 @@ static int adv7180_probe(struct i2c_client *client,
 		return ret;
 	}
 
+	state->rst_gpio = devm_gpiod_get_optional(&client->dev, "reset",
+						  GPIOD_OUT_HIGH);
+	if (IS_ERR(state->rst_gpio)) {
+		ret = PTR_ERR(state->rst_gpio);
+		v4l_err(client, "request for reset pin failed: %d\n", ret);
+		return ret;
+	}
+
+	if (of_property_read_bool(np, "adv,force-bt656-4"))
+		state->force_bt656_4 = true;
+
+	pr_err("%s: force_bt656_4 = %d",__func__,state->force_bt656_4);
+
 	if (state->chip_info->flags & ADV7180_FLAG_MIPI_CSI2) {
 		state->csi_client = i2c_new_dummy_device(client->adapter,
 				ADV7180_DEFAULT_CSI_I2C_ADDR);
 		if (IS_ERR(state->csi_client))
 			return PTR_ERR(state->csi_client);
 	}
-
+	
 	if (state->chip_info->flags & ADV7180_FLAG_I2P) {
 		state->vpp_client = i2c_new_dummy_device(client->adapter,
 				ADV7180_DEFAULT_VPP_I2C_ADDR);
@@ -1392,11 +1652,19 @@ static int adv7180_probe(struct i2c_client *client,
 	if (ret)
 		goto err_free_irq;
 
-	v4l_info(client, "chip found @ 0x%02x (%s)\n",
-		 client->addr, client->adapter->name);
+	mutex_lock(&state->mutex);
+	ret = adv7180_read(state, ADV7180_REG_IDENT);
+	mutex_unlock(&state->mutex);
+	if (ret < 0)
+		goto err_v4l2_async_unregister;
 
+	v4l_info(client, "chip id 0x%x found @ 0x%02x (%s)\n",
+		 ret, client->addr, client->adapter->name);
+	adv7180_test_pattern(state, 1);
 	return 0;
 
+err_v4l2_async_unregister:
+	v4l2_async_unregister_subdev(sd);
 err_free_irq:
 	if (state->irq > 0)
 		free_irq(client->irq, state);
@@ -1417,6 +1685,8 @@ static int adv7180_remove(struct i2c_client *client)
 	struct v4l2_subdev *sd = i2c_get_clientdata(client);
 	struct adv7180_state *state = to_state(sd);
 
+        pr_err("%s: Enter\n",__func__);
+
 	v4l2_async_unregister_subdev(sd);
 
 	if (state->irq > 0)
@@ -1428,6 +1698,7 @@ static int adv7180_remove(struct i2c_client *client)
 	i2c_unregister_device(state->vpp_client);
 	i2c_unregister_device(state->csi_client);
 
+	adv7180_set_reset_pin(state, true);
 	adv7180_set_power_pin(state, false);
 
 	mutex_destroy(&state->mutex);
@@ -1454,20 +1725,20 @@ static int adv7180_remove(struct i2c_client *client)
 #ifdef CONFIG_PM_SLEEP
 static int adv7180_suspend(struct device *dev)
 {
-	struct i2c_client *client = to_i2c_client(dev);
-	struct v4l2_subdev *sd = i2c_get_clientdata(client);
+	struct v4l2_subdev *sd = dev_get_drvdata(dev);
 	struct adv7180_state *state = to_state(sd);
 
+        pr_err("%s: Enter\n",__func__);
 	return adv7180_set_power(state, false);
 }
 
 static int adv7180_resume(struct device *dev)
 {
-	struct i2c_client *client = to_i2c_client(dev);
-	struct v4l2_subdev *sd = i2c_get_clientdata(client);
+	struct v4l2_subdev *sd = dev_get_drvdata(dev);
 	struct adv7180_state *state = to_state(sd);
 	int ret;
 
+        pr_err("%s: Enter\n",__func__);
 	ret = init_device(state);
 	if (ret < 0)
 		return ret;
-- 
1.9.1

We are successfully able to probe the adv7280M and communicated via i2c but i can't seem to get any frames.

Attaching a log for reference

12-31 23:59:59.831     0     0 E mx6s_csi_probe: Enter
12-31 23:59:59.835     0     0 E mx6s-csi 32e20000.csi1_bridge: initialising
12-31 23:59:59.840     0     0 E mx6s_csi_mode_sel: Enter
12-31 23:59:59.843     0     0 E mx6s-csi 32e20000.csi1_bridge: no csi-mux-mipi property found
12-31 23:59:59.850     0     0 E mx6s_csi_two_8bit_sensor_mode_sel: Enter
12-31 23:59:59.856     0     0 E mx6sx_register_subdevs: Enter
12-31 23:59:59.860     0     0 E mipi_csis_probe: Enter
12-31 23:59:59.864     0     0 E mipi_csis_parse_dt: Enter
12-31 23:59:59.867     0     0 E mipi_csis_phy_init: Enter
12-31 23:59:59.871     0     0 W mxc_mipi-csi 32e30000.mipi_csi: supply mipi-phy not found, using dummy regulator
12-31 23:59:59.880     0     0 E mipi_csis_clk_get: Enter
12-31 23:59:59.884     0     0 E mipi_csis_clk_enable: Enter
12-31 23:59:59.887     0     0 E mipi_csis_phy_reset_mx8mm: Enter
12-31 23:59:59.892     0     0 E mxc_mipi-csi 32e30000.mipi_csi: mipi csi v4l2 device registered
12-31 23:59:59.899     0     0 E mipi_csis_subdev_init: Enter
12-31 23:59:59.907     0     0 I CSI     : Registered sensor subdevice: mxc_mipi-csi.0
12-31 23:59:59.913     0     0 E mipi_csis_subdev_host: Enter
12-31 23:59:59.917     0     0 E mipi_csis_clk_disable: Enter
12-31 23:59:59.921     0     0 E mxc_mipi-csi 32e30000.mipi_csi: lanes: 1, hs_settle: 13, clk_settle: 2, wclk: 1, freq: 333000000
01-01 00:00:00.627     0     0 E adv7180_probe: Enter
01-01 00:00:00.630     0     0 E adv7180_probe: force_bt656_4 = 1
01-01 00:00:00.637     0     0 E adv7180_s_ctrl: Enter
01-01 00:00:00.641     0     0 E adv7180_write: Enter reg = 0xa value = 0x0
01-01 00:00:00.646     0     0 E adv7180_select_page: Enter
01-01 00:00:00.653     0     0 E adv7180_set_power_pin: Enter
01-01 00:00:00.657     0     0 E adv7180_set_reset_pin: Enter on = 0
01-01 00:00:00.672     0     0 E adv7180_write: Enter reg = 0xf value = 0x80
01-01 00:00:00.677     0     0 E adv7180_select_page: Enter
01-01 00:00:00.693     0     0 E adv7182_init: Enter
01-01 00:00:00.696     0     0 E adv7182_init: flags = 14, ADV7180_I2P = 8
01-01 00:00:00.696     0     0 E adv7182_init: VPP Slave Addr flags = 14, ADV7180_FLAG_MIPI_CSI2 = 4
01-01 00:00:00.701     0     0 E adv7180_write: Enter reg = 0xfe value = 0x88
01-01 00:00:00.714     0     0 E adv7180_select_page: Enter
01-01 00:00:00.719     0     0 E adv7182_init: VPP Slave Addr flags = 14, ADV7180_I2P = 8
01-01 00:00:00.719     0     0 E adv7180_write: Enter reg = 0xfd value = 0x84
01-01 00:00:00.730     0     0 E adv7180_select_page: Enter
01-01 00:00:00.736     0     0 E adv7180_write: Enter reg = 0x80 value = 0x51
01-01 00:00:00.741     0     0 E adv7180_select_page: Enter
01-01 00:00:00.747     0     0 E adv7180_write: Enter reg = 0x81 value = 0x51
01-01 00:00:00.752     0     0 E adv7180_select_page: Enter
01-01 00:00:00.757     0     0 E adv7180_write: Enter reg = 0x82 value = 0x68
01-01 00:00:00.763     0     0 E adv7180_select_page: Enter
01-01 00:00:00.769     0     0 E adv7180_write: Enter reg = 0x3 value = 0x4e
01-01 00:00:00.774     0     0 E adv7180_select_page: Enter
01-01 00:00:00.780     0     0 E adv7180_write: Enter reg = 0x4 value = 0x57
01-01 00:00:00.785     0     0 E adv7180_select_page: Enter
01-01 00:00:00.790     0     0 E adv7180_write: Enter reg = 0x1d value = 0xc0
01-01 00:00:00.796     0     0 E adv7180_select_page: Enter
01-01 00:00:00.801     0     0 E adv7180_write: Enter reg = 0x13 value = 0x0
01-01 00:00:00.806     0     0 E adv7180_select_page: Enter
01-01 00:00:00.812     0     0 E adv7180_program_std: Enter
01-01 00:00:00.815     0     0 E v4l2_std_to_adv7180: Enter
01-01 00:00:00.819     0     0 E adv7180_set_video_standard: Enter
01-01 00:00:00.824     0     0 E adv7182_set_std: Enter
01-01 00:00:00.827     0     0 E adv7180_write: Enter reg = 0x2 value = 0x50
01-01 00:00:00.832     0     0 E adv7180_select_page: Enter
01-01 00:00:00.838     0     0 E adv7180_set_field_mode: Enter
01-01 00:00:00.842     0     0 E adv7180_set_field_mode: MIPI_CSI2 && V4L2_FIELD_NONE
01-01 00:00:00.842     0     0 E adv7180_csi_write: Enter reg = 0x1 value = 0x20
01-01 00:00:00.855     0     0 E adv7180_csi_write: Enter reg = 0x2 value = 0x28
01-01 00:00:00.861     0     0 E adv7180_csi_write: Enter reg = 0x3 value = 0x38
01-01 00:00:00.869     0     0 E adv7180_csi_write: Enter reg = 0x4 value = 0x30
01-01 00:00:00.876     0     0 E adv7180_csi_write: Enter reg = 0x5 value = 0x30
01-01 00:00:00.883     0     0 E adv7180_csi_write: Enter reg = 0x6 value = 0x80
01-01 00:00:00.890     0     0 E adv7180_csi_write: Enter reg = 0x7 value = 0x70
01-01 00:00:00.897     0     0 E adv7180_csi_write: Enter reg = 0x8 value = 0x50
01-01 00:00:00.903     0     0 E adv7180_vpp_write: Enter reg = 0xa3 value = 0x0
01-01 00:00:00.909     0     0 E adv7180_vpp_write: Enter reg = 0x5b value = 0x0
01-01 00:00:00.916     0     0 E adv7180_vpp_write: Enter reg = 0x55 value = 0x80
01-01 00:00:00.923     0     0 E adv7180_set_field_mode: I2P Core Enabled
01-01 00:00:00.932     0     0 E mxc_mipi-csi 32e30000.mipi_csi: Registered sensor subdevice: adv7180 1-0021
01-01 00:00:00.940     0     0 E adv7180_read: Enter reg = 11
01-01 00:00:00.944     0     0 E adv7180_select_page: Enter
01-01 00:00:00.949     0     0 I adv7180 1-0021: chip id 0x43 found @ 0x21 (30a30000.i2c)
01-01 00:00:00.956     0     0 E adv7180_test_pattern: Enter
01-01 00:00:00.959     0     0 E adv7180_write: Enter reg = 0x14 value = 0x1
01-01 00:00:00.965     0     0 E adv7180_select_page: Enter
01-01 00:00:00.969     0     0 E adv7180_read: Enter reg = c
01-01 00:00:00.973     0     0 E adv7180_select_page: Enter
01-01 00:00:00.979     0     0 E adv7180_write: Enter reg = 0xc value = 0x37
01-01 00:00:00.984     0     0 E adv7180_select_page: Enter
01-01 00:00:01.725     0     0 I imx_sec_dsim_drv 32e10000.mipi_dsi: version number is 0x1060200
01-01 00:00:01.732     0     0 I imx-drm 32c00000.bus: display-subsystem: bound 32e10000.mipi_dsi (ops imx_sec_dsim_ops)
01-01 00:00:15.322     0     0 E mx6s_csi_open: Enter
01-01 00:00:15.326     0     0 E mx6s_csi_open: Enter
01-01 00:00:15.329     0     0 E mx6s-csi 32e20000.csi1_bridge: csi v4l2 busfreq high request.
01-01 00:00:15.336     0     0 E mipi_csis_s_power: Enter
01-01 00:00:15.343     0     0 E adv7180_s_power: Enter
01-01 00:00:15.347     0     0 E adv7180_set_power: Enter
01-01 00:00:15.350     0     0 E adv7180_write: Enter reg = 0xf value = 0x4
01-01 00:00:15.356     0     0 E adv7180_select_page: Enter
01-01 00:00:15.360     0     0 E adv7180_csi_write: Enter reg = 0xde value = 0x2
01-01 00:00:15.367     0     0 E adv7180_csi_write: Enter reg = 0xd2 value = 0xf7
01-01 00:00:15.373     0     0 E adv7180_csi_write: Enter reg = 0xd8 value = 0x65
01-01 00:00:15.379     0     0 E adv7180_csi_write: Enter reg = 0xe0 value = 0x9
01-01 00:00:15.385     0     0 E adv7180_csi_write: Enter reg = 0x2c value = 0x0
01-01 00:00:15.392     0     0 E adv7180_csi_write: Enter reg = 0x1d value = 0x80
01-01 00:00:15.399     0     0 E adv7180_csi_write: Enter reg = 0x0 value = 0x0
01-01 00:00:15.410     0     0 E mipi_csis_pm_resume: Enter
01-01 00:00:15.415     0     0 E mxc_mipi-csi.0: mipi_csis_pm_resume: flags: 0x0
01-01 00:00:15.417     0     0 E mx6s_csi_open: Enter
01-01 00:00:15.421     0     0 E mipi_csis_clk_enable: Enter
01-01 00:00:15.424     0     0 E mx6s_csi_open: Enter
01-01 00:00:15.428     0     0 E mx6s_mx6s_csi_init: Enter
01-01 00:00:15.435     0     0 E mx6s_csi_clk_enable: Enter, clk_csi_mclk = ffff0000c12f8800
01-01 00:00:15.442     0     0 E mx6s_csihw_reset: Enter
01-01 00:00:15.446     0     0 E mx6s_csi_init_interface: Enter
01-01 00:00:15.451     0     0 E mx6s_csi_dmareq_rff_disable: Enter
01-01 00:00:15.459     0     0 E mx6s_csi_open: Exit
01-01 00:00:15.463     0     0 E mx6s_vidioc_querycap: Enter
01-01 00:00:15.473     0     0 E mx6s_vidioc_querycap: platform: 32e20000.csi1_bridge
01-01 00:00:15.474     0     0 E mx6s_csi_close: Enter
01-01 00:00:15.484     0     0 E mx6s_csi_close: Enter
01-01 00:00:15.491     0     0 E mx6s_mx6s_csi_deinit: Enter
01-01 00:00:15.519     0     0 E mx6s_csihw_reset: Enter
01-01 00:00:15.523     0     0 E mx6s_csi_init_interface: Enter
01-01 00:00:15.544     0     0 E mx6s_csi_dmareq_rff_disable: Enter
01-01 00:00:15.595     0     0 E mx6s_csi_clk_disable: Enter
01-01 00:00:15.599     0     0 E mipi_csis_s_power: Enter
01-01 00:00:15.758     0     0 E adv7180_s_power: Enter
01-01 00:00:15.815     0     0 E adv7180_set_power: Enter
01-01 00:00:16.004     0     0 E adv7180_write: Enter reg = 0xf value = 0x24
01-01 00:00:16.026     0     0 E adv7180_select_page: Enter
01-01 00:00:16.051     0     0 E adv7180_csi_write: Enter reg = 0x0 value = 0x80
01-01 00:00:16.084     0     0 E mipi_csis_pm_suspend: Enter
01-01 00:00:16.088     0     0 E mxc_mipi-csi.0: mipi_csis_pm_suspend: flags: 0x1
01-01 00:00:16.104     0     0 E mipi_csis_stop_stream: Enter
01-01 00:00:16.108     0     0 E mipi_csis_enable_interrupts: Enter
01-01 00:00:16.113     0     0 E mipi_csis_system_enable: Enter
01-01 00:00:16.117     0     0 E mipi_csis_clk_disable: Enter
01-01 00:00:16.121     0     0 E mx6s-csi 32e20000.csi1_bridge: csi v4l2 busfreq high release.
01-01 00:00:16.128     0     0 E mx6s_csi_close: Exit
01-01 00:00:16.131     0     0 E mx6s-csi 32e20000.csi1_bridge: csi v4l2 busfreq high request.
01-01 00:00:16.131     0     0 E mipi_csis_s_power: Enter
01-01 00:00:16.131     0     0 E adv7180_s_power: Enter
01-01 00:00:16.131     0     0 E adv7180_set_power: Enter
01-01 00:00:16.131     0     0 E adv7180_write: Enter reg = 0xf value = 0x4
01-01 00:00:16.131     0     0 E adv7180_select_page: Enter
01-01 00:00:16.150     0     0 E adv7180_csi_write: Enter reg = 0xde value = 0x2
01-01 00:00:16.162     0     0 E mx6s_csi_open: Enter
01-01 00:00:16.164     0     0 E adv7180_csi_write: Enter reg = 0xd2 value = 0xf7
01-01 00:00:16.167     0     0 E mx6s_csi_open: Enter
01-01 00:00:16.170     0     0 E adv7180_csi_write: Enter reg = 0xd8 value = 0x65
01-01 00:00:16.203     0     0 E adv7180_csi_write: Enter reg = 0xe0 value = 0x9
01-01 00:00:16.209     0     0 E adv7180_csi_write: Enter reg = 0x2c value = 0x0
01-01 00:00:16.215     0     0 E adv7180_csi_write: Enter reg = 0x1d value = 0x80
01-01 00:00:16.221     0     0 E adv7180_csi_write: Enter reg = 0x0 value = 0x0
01-01 00:00:16.227     0     0 E mipi_csis_pm_resume: Enter
01-01 00:00:16.231     0     0 E mxc_mipi-csi.0: mipi_csis_pm_resume: flags: 0x0
01-01 00:00:16.237     0     0 E mipi_csis_clk_enable: Enter
01-01 00:00:16.241     0     0 E mx6s_mx6s_csi_init: Enter
01-01 00:00:16.245     0     0 E mx6s_csi_clk_enable: Enter, clk_csi_mclk = ffff0000c12f8800
01-01 00:00:16.251     0     0 E mx6s_csihw_reset: Enter
01-01 00:00:16.255     0     0 E mx6s_csi_init_interface: Enter
01-01 00:00:16.259     0     0 E mx6s_csi_dmareq_rff_disable: Enter
01-01 00:00:16.263     0     0 E mx6s_csi_open: Exit
01-01 00:00:16.263     0     0 E mx6s_csi_open: Exit
01-01 00:00:16.267     0     0 E mx6s_vidioc_querycap: Enter
01-01 00:00:16.274     0     0 E mx6s_vidioc_querycap: platform: 32e20000.csi1_bridge
01-01 00:00:16.274     0     0 E mx6s_vidioc_enum_framesizes: Enter
01-01 00:00:16.274     0     0 E mx6s_csi_close: Enter
01-01 00:00:16.280     0     0 E mx6s_format_by_fourcc: Enter
01-01 00:00:16.292     0     0 E mx6s_format_by_fourcc: pixelformat:'YUYV'
01-01 00:00:16.297     0     0 E mipi_csis_enum_framesizes: Enter
01-01 00:00:16.301     0     0 E adv7180_enum_frame_size: Enter
01-01 00:00:16.306     0     0 E mx6s_vidioc_enum_framesizes: ret = 0 fsize->index = 0
01-01 00:00:16.306     0     0 E mx6s_vidioc_enum_framesizes: fse: min_width = 720 min_height = 480 max_width = 720 max_height = 480
01-01 00:00:16.328     0     0 E mx6s_csi_close: Enter
01-01 00:00:16.331     0     0 E mx6s_csi_close: Exit
01-01 00:00:16.331     0     0 E mx6s_vidioc_enum_frameintervals: Enter
01-01 00:00:16.340     0     0 E mx6s_format_by_fourcc: Enter
01-01 00:00:16.344     0     0 E mx6s_format_by_fourcc: pixelformat:'YUYV'
01-01 00:00:16.349     0     0 E mipi_csis_enum_frameintervals: Enter
01-01 00:00:16.354     0     0 E adv7180_enum_frame_interval: Enter
01-01 00:00:16.358     0     0 E mx6s_vidioc_enum_framesizes: Enter
01-01 00:00:16.363     0     0 E mx6s_format_by_fourcc: Enter
01-01 00:00:16.367     0     0 E mx6s_format_by_fourcc: pixelformat:'YUYV'
01-01 00:00:16.372     0     0 E mipi_csis_enum_framesizes: Enter
01-01 00:00:16.377     0     0 E adv7180_enum_frame_size: Enter
01-01 00:00:16.381     0     0 E mx6s_vidioc_enum_framesizes: ret = -22 fsize->index = 1
01-01 00:00:16.381     0     0 E mx6s_vidioc_enum_framesizes: fse: min_width = 0 min_height = 0 max_width = 0 max_height = 0
01-01 00:00:16.397     0     0 E mx6s_vidioc_enum_framesizes: return ret
01-01 00:00:16.397     0     0 E mx6s_csi_close: Enter
01-01 00:00:16.405     0     0 E mx6s_csi_close: Enter
01-01 00:00:16.409     0     0 E mx6s_mx6s_csi_deinit: Enter
01-01 00:00:16.413     0     0 E mx6s_csihw_reset: Enter
01-01 00:00:16.416     0     0 E mx6s_csi_init_interface: Enter
01-01 00:00:16.420     0     0 E mx6s_csi_dmareq_rff_disable: Enter
01-01 00:00:16.425     0     0 E mx6s_csi_clk_disable: Enter
01-01 00:00:16.429     0     0 E mipi_csis_s_power: Enter
01-01 00:00:16.435     0     0 E adv7180_s_power: Enter
01-01 00:00:16.439     0     0 E adv7180_set_power: Enter
01-01 00:00:16.442     0     0 E adv7180_write: Enter reg = 0xf value = 0x24
01-01 00:00:16.448     0     0 E adv7180_select_page: Enter
01-01 00:00:16.452     0     0 E adv7180_csi_write: Enter reg = 0x0 value = 0x80
01-01 00:00:16.458     0     0 E mipi_csis_pm_suspend: Enter
01-01 00:00:16.462     0     0 E mxc_mipi-csi.0: mipi_csis_pm_suspend: flags: 0x1
01-01 00:00:16.468     0     0 E mipi_csis_stop_stream: Enter
01-01 00:00:16.472     0     0 E mipi_csis_enable_interrupts: Enter
01-01 00:00:16.477     0     0 E mipi_csis_system_enable: Enter
01-01 00:00:16.481     0     0 E mipi_csis_clk_disable: Enter
01-01 00:00:16.485     0     0 E mx6s-csi 32e20000.csi1_bridge: csi v4l2 busfreq high release.
01-01 00:00:16.492     0     0 E mx6s_csi_close: Exit
08-08 08:55:48.839     0     0 E mx6s_csi_open: Enter
08-08 08:55:48.843     0     0 E mx6s_csi_open: Enter
08-08 08:55:48.846     0     0 E mx6s-csi 32e20000.csi1_bridge: csi v4l2 busfreq high request.
08-08 08:55:48.853     0     0 E mipi_csis_s_power: Enter
08-08 08:55:48.859     0     0 E adv7180_s_power: Enter
08-08 08:55:48.863     0     0 E adv7180_set_power: Enter
08-08 08:55:48.867     0     0 E adv7180_write: Enter reg = 0xf value = 0x4
08-08 08:55:48.872     0     0 E adv7180_select_page: Enter
08-08 08:55:48.876     0     0 E adv7180_csi_write: Enter reg = 0xde value = 0x2
08-08 08:55:48.882     0     0 E adv7180_csi_write: Enter reg = 0xd2 value = 0xf7
08-08 08:55:48.888     0     0 E adv7180_csi_write: Enter reg = 0xd8 value = 0x65
08-08 08:55:48.894     0     0 E adv7180_csi_write: Enter reg = 0xe0 value = 0x9
08-08 08:55:48.900     0     0 E adv7180_csi_write: Enter reg = 0x2c value = 0x0
08-08 08:55:48.906     0     0 E adv7180_csi_write: Enter reg = 0x1d value = 0x80
08-08 08:55:48.913     0     0 E adv7180_csi_write: Enter reg = 0x0 value = 0x0
08-08 08:55:48.919     0     0 E mipi_csis_pm_resume: Enter
08-08 08:55:48.922     0     0 E mxc_mipi-csi.0: mipi_csis_pm_resume: flags: 0x0
08-08 08:55:48.928     0     0 E mipi_csis_clk_enable: Enter
08-08 08:55:48.932     0     0 E mx6s_mx6s_csi_init: Enter
08-08 08:55:48.936     0     0 E mx6s_csi_clk_enable: Enter, clk_csi_mclk = ffff0000c12f8800
08-08 08:55:48.942     0     0 E mx6s_csihw_reset: Enter
08-08 08:55:48.946     0     0 E mx6s_csi_init_interface: Enter
08-08 08:55:48.950     0     0 E mx6s_csi_dmareq_rff_disable: Enter
08-08 08:55:48.954     0     0 E mx6s_csi_open: Exit
08-08 08:55:48.958     0     0 E mx6s_vidioc_querycap: Enter
08-08 08:55:48.962     0     0 E mx6s_vidioc_querycap: platform: 32e20000.csi1_bridge
08-08 08:55:48.962     0     0 E mx6s_csi_close: Enter
08-08 08:55:48.971     0     0 E mx6s_csi_close: Enter
08-08 08:55:48.974     0     0 E mx6s_mx6s_csi_deinit: Enter
08-08 08:55:48.978     0     0 E mx6s_csihw_reset: Enter
08-08 08:55:48.982     0     0 E mx6s_csi_init_interface: Enter
08-08 08:55:48.986     0     0 E mx6s_csi_dmareq_rff_disable: Enter
08-08 08:55:48.990     0     0 E mx6s_csi_clk_disable: Enter
08-08 08:55:48.994     0     0 E mipi_csis_s_power: Enter
08-08 08:55:49.001     0     0 E adv7180_s_power: Enter
08-08 08:55:49.004     0     0 E adv7180_set_power: Enter
08-08 08:55:49.008     0     0 E adv7180_write: Enter reg = 0xf value = 0x24
08-08 08:55:49.013     0     0 E adv7180_select_page: Enter
08-08 08:55:49.018     0     0 E adv7180_csi_write: Enter reg = 0x0 value = 0x80
08-08 08:55:49.024     0     0 E mipi_csis_pm_suspend: Enter
08-08 08:55:49.028     0     0 E mxc_mipi-csi.0: mipi_csis_pm_suspend: flags: 0x1
08-08 08:55:49.034     0     0 E mipi_csis_stop_stream: Enter
08-08 08:55:49.038     0     0 E mipi_csis_enable_interrupts: Enter
08-08 08:55:49.042     0     0 E mipi_csis_system_enable: Enter
08-08 08:55:49.046     0     0 E mipi_csis_clk_disable: Enter
08-08 08:55:49.050     0     0 E mx6s-csi 32e20000.csi1_bridge: csi v4l2 busfreq high release.
08-08 08:55:49.057     0     0 E mx6s_csi_close: Exit
08-08 08:56:06.429     0     0 E mx6s_csi_open: Enter
08-08 08:56:06.432     0     0 E mx6s_csi_open: Enter
08-08 08:56:06.464     0     0 E mx6s-csi 32e20000.csi1_bridge: csi v4l2 busfreq high request.
08-08 08:56:06.483     0     0 E mipi_csis_s_power: Enter
08-08 08:56:06.513     0     0 E adv7180_s_power: Enter
08-08 08:56:06.520     0     0 E adv7180_set_power: Enter
08-08 08:56:06.524     0     0 E adv7180_write: Enter reg = 0xf value = 0x4
08-08 08:56:06.559     0     0 E adv7180_select_page: Enter
08-08 08:56:06.592     0     0 E adv7180_csi_write: Enter reg = 0xde value = 0x2
08-08 08:56:06.603     0     0 E adv7180_csi_write: Enter reg = 0xd2 value = 0xf7
08-08 08:56:06.612     0     0 E adv7180_csi_write: Enter reg = 0xd8 value = 0x65
08-08 08:56:06.620     0     0 E adv7180_csi_write: Enter reg = 0xe0 value = 0x9
08-08 08:56:06.628     0     0 E adv7180_csi_write: Enter reg = 0x2c value = 0x0
08-08 08:56:06.636     0     0 E adv7180_csi_write: Enter reg = 0x1d value = 0x80
08-08 08:56:06.644     0     0 E adv7180_csi_write: Enter reg = 0x0 value = 0x0
08-08 08:56:06.652     0     0 E mipi_csis_pm_resume: Enter
08-08 08:56:06.657     0     0 E mxc_mipi-csi.0: mipi_csis_pm_resume: flags: 0x0
08-08 08:56:06.665     0     0 E mipi_csis_clk_enable: Enter
08-08 08:56:06.670     0     0 E mx6s_mx6s_csi_init: Enter
08-08 08:56:06.675     0     0 E mx6s_csi_clk_enable: Enter, clk_csi_mclk = ffff0000c12f8800
08-08 08:56:06.682     0     0 E mx6s_csihw_reset: Enter
08-08 08:56:06.687     0     0 E mx6s_csi_init_interface: Enter
08-08 08:56:06.692     0     0 E mx6s_csi_dmareq_rff_disable: Enter
08-08 08:56:06.701     0     0 E mx6s_csi_open: Exit
08-08 08:56:07.083     0     0 E mx6s_vidioc_enum_framesizes: Enter
08-08 08:56:07.087     0     0 E mx6s_format_by_fourcc: Enter
08-08 08:56:07.091     0     0 E mx6s_format_by_fourcc: pixelformat:'YUYV'
08-08 08:56:07.096     0     0 E mipi_csis_enum_framesizes: Enter
08-08 08:56:07.101     0     0 E adv7180_enum_frame_size: Enter
08-08 08:56:07.105     0     0 E mx6s_vidioc_enum_framesizes: ret = 0 fsize->index = 0
08-08 08:56:07.105     0     0 E mx6s_vidioc_enum_framesizes: fse: min_width = 720 min_height = 480 max_width = 720 max_height = 480
08-08 08:56:07.127     0     0 E mx6s_vidioc_enum_frameintervals: Enter
08-08 08:56:07.133     0     0 E mx6s_format_by_fourcc: Enter
08-08 08:56:07.137     0     0 E mx6s_format_by_fourcc: pixelformat:'YUYV'
08-08 08:56:07.142     0     0 E mipi_csis_enum_frameintervals: Enter
08-08 08:56:07.147     0     0 E adv7180_enum_frame_interval: Enter
08-08 08:56:07.151     0     0 E mx6s_vidioc_enum_frameintervals: Enter
08-08 08:56:07.156     0     0 E mx6s_format_by_fourcc: Enter
08-08 08:56:07.160     0     0 E mx6s_format_by_fourcc: pixelformat:'YUYV'
08-08 08:56:07.165     0     0 E mipi_csis_enum_frameintervals: Enter
08-08 08:56:07.170     0     0 E adv7180_enum_frame_interval: Enter
08-08 08:56:07.175     0     0 E mx6s_vidioc_s_parm: Enter
08-08 08:56:07.179     0     0 E mipi_csis_s_parm: Enter
08-08 08:56:07.183     0     0 E adv7180_s_parm: Enter
08-08 08:56:07.186     0     0 E mx6s_vidioc_s_fmt_vid_cap: Enter
08-08 08:56:07.191     0     0 E mx6s_vidioc_try_fmt_vid_cap: Enter
08-08 08:56:07.195     0     0 E mx6s_format_by_fourcc: Enter
08-08 08:56:07.199     0     0 E mx6s_format_by_fourcc: pixelformat:'YUYV'
08-08 08:56:07.205     0     0 E mx6s_vidioc_try_fmt_vid_cap: pixelformat = 0x56595559
08-08 08:56:07.211     0     0 E _mx6s_vidioc_try_fmt_vid_cap: width = 720 height = 480 field = 0
08-08 08:56:07.218     0     0 E mipi_csis_set_fmt: Enter
08-08 08:56:07.222     0     0 E find_csis_format: mipi_csis formats = 296829964
08-08 08:56:07.230     0     0 E adv7180_set_pad_format: Enter format->format.field = 0
08-08 08:56:07.237     0     0 E adv7180_set_pad_format: V4L2_FIELD_NONE fallthrough set
08-08 08:56:07.237     0     0 E adv7180_set_pad_format: Final format->format.field = 1
08-08 08:56:07.252     0     0 E adv7180_mbus_fmt: Enter
08-08 08:56:07.256     0     0 E adv7180_set_pad_format: V4L2_SUBDEV_FORMAT_ACTIVE
08-08 08:56:07.256     0     0 E mx6s_vidioc_try_fmt_vid_cap: NOT INTERLACED defaulting to NONE
08-08 08:56:07.262     0     0 E mx6s_vidioc_s_fmt_vid_cap: csi_dev->pix.field = 0 f->fmt.pix.field = 1
08-08 08:56:07.269     0     0 E mx6s_format_by_fourcc: Enter
08-08 08:56:07.281     0     0 E mx6s_format_by_fourcc: pixelformat:'YUYV'
08-08 08:56:07.286     0     0 E mx6s-csi 32e20000.csi1_bridge: set to pixelformat 'YUYV-1'
08-08 08:56:07.292     0     0 E mx6s_configure_csi: Enter
08-08 08:56:07.296     0     0 E mx6s_csi_deinterlace_enable: Enter
08-08 08:56:07.301     0     0 E mx6s_csi_buf_stride_set: Enter
08-08 08:56:07.305     0     0 E mx6s_csi_set_imagpara: Enter
08-08 08:56:07.328     0     0 E mx6s_vidioc_reqbufs: Enter
08-08 08:56:07.332     0     0 E mx6s_mx6s_videobuf_setup: Enter
08-08 08:56:07.336     0     0 E mx6s-csi 32e20000.csi1_bridge: count=3, size=0
08-08 08:56:07.357     0     0 E mx6s_vidioc_querybuf: Enter
08-08 08:56:07.378     0     0 E mx6s_vidioc_querybuf: Enter
08-08 08:56:07.383     0     0 E mx6s_vidioc_qbuf: Enter
08-08 08:56:07.387     0     0 E mx6s_mx6s_videobuf_prepare: Enter
08-08 08:56:07.391     0     0 E mx6s-csi 32e20000.csi1_bridge: mx6s_videobuf_prepare (vb=0x00000000276a0d0e) 0x00000000cbf70a8a 0
08-08 08:56:07.401     0     0 E mx6s_vidioc_qbuf: Enter
08-08 08:56:07.405     0     0 E mx6s_mx6s_videobuf_prepare: Enter
08-08 08:56:07.410     0     0 E mx6s-csi 32e20000.csi1_bridge: mx6s_videobuf_prepare (vb=0x00000000c4ca2ee7) 0x00000000aa025cc5 0
08-08 08:56:07.420     0     0 E mx6s_vidioc_qbuf: Enter
08-08 08:56:07.423     0     0 E mx6s_mx6s_videobuf_prepare: Enter
08-08 08:56:07.428     0     0 E mx6s-csi 32e20000.csi1_bridge: mx6s_videobuf_prepare (vb=0x00000000a0e68db8) 0x000000004c5e6c8b 0
08-08 08:56:07.438     0     0 E mx6s_vidioc_streamon: Enter
08-08 08:56:07.442     0     0 E mx6s_mx6s_videobuf_queue: Enter
08-08 08:56:07.446     0     0 E mx6s-csi 32e20000.csi1_bridge: mx6s_videobuf_queue (vb=0x00000000276a0d0e) 0x00000000cbf70a8a 691200
08-08 08:56:07.456     0     0 E mx6s_mx6s_videobuf_queue: Enter
08-08 08:56:07.461     0     0 E mx6s-csi 32e20000.csi1_bridge: mx6s_videobuf_queue (vb=0x00000000c4ca2ee7) 0x00000000aa025cc5 691200
08-08 08:56:07.471     0     0 E mx6s_mx6s_videobuf_queue: Enter
08-08 08:56:07.475     0     0 E mx6s-csi 32e20000.csi1_bridge: mx6s_videobuf_queue (vb=0x00000000a0e68db8) 0x000000004c5e6c8b 691200
08-08 08:56:07.485     0     0 E mx6s_start_streaming: Enter
08-08 08:56:07.495     0     0 E mx6s_update_csi_buf: Enter buf number = 0, phys = 2455764992
08-08 08:56:07.507     0     0 E mx6s_update_csi_buf: Enter buf number = 1, phys = 2461007872
08-08 08:56:07.519     0     0 E mx6s_csi_enable: Enter
08-08 08:56:07.522     0     0 E mx6s_csisw_reset: Enter
08-08 08:56:07.598     0     0 E mx6s_csi_enable: csi_tvdec_enable false
08-08 08:56:07.603     0     0 E mx6s_csi_dmareq_rff_enable: Enter
08-08 08:56:07.608     0     0 E mx6s_csi_enable_int: Enter
08-08 08:56:07.612     0     0 E mx6s_csi_enable: Enter
08-08 08:56:07.615     0     0 E mipi_csis_s_stream: Enter
08-08 08:56:07.619     0     0 E mxc_mipi-csi.0: mipi_csis_s_stream: 1, state: 0x1
08-08 08:56:07.625     0     0 E mipi_csis_clear_counters: Enter
08-08 08:56:07.629     0     0 E mipi_csis_start_stream: Enter
08-08 08:56:07.634     0     0 E mipi_csis_sw_reset: Enter
08-08 08:56:07.638     0     0 E mipi_csis_set_params: Enter
08-08 08:56:07.642     0     0 E __mipi_csis_set_format: Enter
08-08 08:56:07.646     0     0 E mxc_mipi-csi.0: fmt: 0x2008, 720 x 480
08-08 08:56:07.651     0     0 E mipi_csis_set_hsync_settle: Enter
08-08 08:56:07.655     0     0 E mipi_csis_system_enable: Enter
08-08 08:56:07.659     0     0 E mipi_csis_enable_interrupts: Enter
08-08 08:56:07.664     0     0 E mxc_mipi-csi.0: --- mipi_csis_start_stream ---
08-08 08:56:07.670     0     0 E mxc_mipi-csi.0: CTRL: 0x03060301
08-08 08:56:07.674     0     0 E mxc_mipi-csi.0: DPHYCTRL: 0x00004005
08-08 08:56:07.679     0     0 E mxc_mipi-csi.0: CONFIG: 0x000f0000
08-08 08:56:07.684     0     0 E mxc_mipi-csi.0: DPHYSTS: 0xdeadcafe
08-08 08:56:07.689     0     0 E mxc_mipi-csi.0: INTMSK: 0xf00fffff
08-08 08:56:07.694     0     0 E mxc_mipi-csi.0: RESOL: 0xdeadcafe
08-08 08:56:07.699     0     0 E mxc_mipi-csi.0: SDW_CONFIG: 0x00000000
08-08 08:56:07.707     0     0 E adv7180_s_stream: Enter
08-08 08:56:07.712     0     0 E mx6s_vidioc_dqbuf: Enter

Please let us know if we are missing something in the changes.

Lastly we can see the CSI CLK at 218 Mhz on the oscilloscope (Progressive output) and some signals on the data lines too, but no output on android camera app.

  • Hi,

    Please make sure with below things,

     1) Make sure whether ADV7280-M is programmed correctly with ADI recommended  I2C writes,

     2) Could you ensure that during power-up: the reset pin is held low for at least 5ms after the 3.3V, 1.8V and powerdown lines go high. After the reset pin goes high, wait for at least 5ms before starting I2C communication.

     3) After programming the ADV7280-M  could you please read the User Map register 0x0F. This should have the value 0x00.

     4) Can you ensure that there is no contention on the lines. i.e. that the backend processor could be trying to pull the line low as the ADV7280-M tries to output a MIPI clock.

     5) The backend processor is not configured correctly and it is pulling the clock lane low. Could you double check that the backend processor is configured correctly with latest software.

      Expert written an applications note describing the main issues interfacing the ADV728x with a MIPI receiver. Please refer the link here: https://www.analog.com/media/en/technical-documentation/application-notes/AN-1337.pdf
    And also please check that the reset and power-down pins are controlled in the manner described in the datasheet "optimal power-up sequence" section.

    Also please check freescale forum ADV7181 on IMX6Q board | Freescale Community

    Note:  As part of the MIPI specification the MIPI receiver needs to terminate the signals correctly. The termination required changes depending on the MIPI mode (e.g. high speed, low power mode etc). The receiver needs to detect the mode of operation and dynamically set its termination accordingly.

    Note that the Clock signals will only appear correctly when properly terminated.Until proper termination is achieved then you will not be able to decode video data from the MIPI CSI-2 signals output by the ADV7280-M.

    Thanks,

    Poornima

  •  1) Make sure whether ADV7280-M is programmed correctly with ADI recommended  I2C writes

    * We are using default driver provided in the mainline linux, please see below.

    https://source.codeaurora.org/external/imx/linux-imx/tree/drivers/media/i2c/adv7180.c?h=android-11.0.0_2.2.0

     * we have made the changes to enable progressive scanning. V4L2_FIELD_ALTERNATE was changed to  V4L2_FIELD_NONE in the probe function as suggest in this commit message of this patch:

    https://source.codeaurora.org/external/imx/linux-imx/commit/drivers/media/i2c/adv7180.c?h=android-11.0.0_2.2.0&id=851a54effbd808daf8b961f1dc6156c06a96d5f1

     2) Could you ensure that during power-up: the reset pin is held low for at least 5ms after the 3.3V, 1.8V and powerdown lines go high. After the reset pin goes high, wait for at least 5ms before starting I2C communication.

     * Yes we have cross verified the boot up sequence. but we are following the SIMPLIFIED POWER-UP SEQUENCE. we are able to communicate with with ADV through I2C and read write all the required register values. refer below attached image for reference.

     3) After programming the ADV7280-M  could you please read the User Map register 0x0F. This should have the value 0x00.

       * We are able to communicate with I2C of ADV7280M to get and set regs. We are getting the value 0x04 on 0x0F(which is 0000 0100 in binary, where 0x0F(5) is "0") and even if we override it to 0x00 there is no change in the output. 

     4) Can you ensure that there is no contention on the lines. i.e. that the backend processor could be trying to pull the line low as the ADV7280-M tries to output a MIPI clock.

      * No we have cross verified and the imx is not trying to pull any lines low. Can you be specify regarding what "line"  are we talking about here. we have checked MIPI Clk and data, reset and power down (directly connected to VCC as shown in the schematics previously shared). Can you please verify the patch for the integration of adv7280M which is previously shared and let us know if there is any changes required 

     5) The backend processor is not configured correctly and it is pulling the clock lane low. Could you double check that the backend processor is configured correctly with latest software.

      Expert written an applications note describing the main issues interfacing the ADV728x with a MIPI receiver. Please refer the link here: https://www.analog.com/media/en/technical-documentation/application-notes/AN-1337.pdf
    And also please check that the reset and power-down pins are controlled in the manner described in the datasheet "optimal power-up sequence" section.

    *  We are following the SIMPLIFIED POWER-UP SEQUENCE and  there is no backend processor pulling the any lines low. We are able to see continuous clock and data signal on the CSI CLK and CSI Data Lines once camera is enabled.

    Also please check freescale forum ADV7181 on IMX6Q board | Freescale Community

    Note:  As part of the MIPI specification the MIPI receiver needs to terminate the signals correctly. The termination required changes depending on the MIPI mode (e.g. high speed, low power mode etc). The receiver needs to detect the mode of operation and dynamically set its termination accordingly.

    Note that the Clock signals will only appear correctly when properly terminated.Until proper termination is achieved then you will not be able to decode video data from the MIPI CSI-2 signals output by the ADV7280-M.

     *  Can you please elaborate on the MIPI termination and the impedance setting on CSI side 

    NOTE: the url ADV7181 on IMX6Q board | Freescale Community is not valid can you please share a valid url again. 

    Please find the wave forms below 

    Power-on up sequence

    CSI CLK 

    CSI DATA

    ADV7280M Crystal clk 

    Please let us know if any more details are needed. 

  • Hi,

       Please find the below comments,

     1)    Could you please crosscheck your driver configuration at Linux Drivers [Analog Devices Wiki] (ADI linux drivers)

     The Linux driver for the ADV7280 branch in the Linux kernel git repository on the ADI github account.

    https://github.com/analogdevicesinc/linux/tree/adv7280

    https://github.com/analogdevicesinc/linux/blob/adv7280/drivers/media/i2c/adv7180.c

    This driver support parts for both adv718x and adv728x family.

    Also ADV7282-M driver is part of the upstream Linux kernel distribution and can be found at http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/drivers/media/i2c/adv7180.c

    4) We are talking about MIPI clock lines to ensure whether the backend processor is making the line as low.

    Also Please ensure with your backend processor is waiting for a low power (LP) to high speed (HS) transition on the MIPI clock lanes on the ADV7280-M. By default the ADV7280-M will only perform a LP -> HS transition once after it has been configured. It will then remain in HS mode.

    We can force a LP-> HS transition by setting the CSI Map register 0x00 to the value 0x80 and then back to the value 0x00.

    5)  MIPI Termination:

    You can use the University of New Hampshire MIPI reference termination board.

    For our evaluation of the ADV7280-M We used the MIPI reference termination board which is available from here:
    MIPI Test Boards | InterOperability Laboratory

     When you terminate the output signals from the ADV7280-M (in a micro processor/ FPGA) then you will see the correct MIPI traces. Note that the Micro processor/ FPGA needs to be able to detect the output format (high speed mode or low power mode) and dynamically change its input impedance. If the micro processor/ FPGA does not control the termination correctly then the MIPI signals from the ADV7280-M cannot be decoded.

    I believe that your MIPI receiver (micro processor/ FPGA) has not been configured correctly.

    This is described in applications note AN-1337

    http://www.analog.com/media/en/technical-documentation/application-notes/AN-1337.pdf

    Ensure the proper clock rate(27Mhz) has given. All filtering and termination is performed in the D-PHY layer of the ADV7280-M,ADV7281-M, ADV7281-MA, and ADV7282-M transmitter devices and in the D-PHY layer of the MIPI CSI-2 receiver. Do not place additional components, such as resistors,electrostatic discharge (ESD) diodes, capacitors, or common-mode chokes on the MIPI CSI-2 traces.
    Please ensure with good ground connections on the board i. ground plane.

    As per expert comment, PVDD is very important for maintaining the video stability.

      Ideally it should be ferrite bead isolated from other supplies and the data sheet reference schematic does not show this which is OK if the PVDD source is very clean. 

      First check PVDD noise both high frequency and lower frequencies around the horizontal rates.  If noise is coupled into PVDD then the PLL might lose lock and causing image issues.

    Also make sure with below things,

     1) First verify the PVDD_1.8V for the ELPF remains stable and clean when the problem shows up.

     2) Check that all voltages are clean and stable.

     3) Try C0G (NPO) material caps and see if that resolves the issue.

    Note: In low power mode the termination needed is 50Ohm single ended. In high speed mode termination needed is 100 Ohm differential. Please refer reference schematic at (+) ADV7281/ADV7281-M / ADV7281-MA Design Support Files - Documents - Video - EngineerZone (analog.com)

    Please refer freescale community at Home - NXP Community

    Thanks,

    Poornima

  • Hi Poornima,

    please see our responses below starting with " *** "

    Hi,

       Please find the below comments,

     1)    Could you please crosscheck your driver configuration at Linux Drivers [Analog Devices Wiki] (ADI linux drivers)

     The Linux driver for the ADV7280 branch in the Linux kernel git repository on the ADI github account.

    https://github.com/analogdevicesinc/linux/tree/adv7280

    https://github.com/analogdevicesinc/linux/blob/adv7280/drivers/media/i2c/adv7180.c

    This driver support parts for both adv718x and adv728x family.

    Also ADV7282-M driver is part of the upstream Linux kernel distribution and can be found at http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/drivers/media/i2c/adv7180.c

    *** Yes, we have used the same driver you mentioned: http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/drivers/media/i2c/adv7180.c

    4)  We are talking about MIPI clock lines to ensure whether the backend processor is making the line as low.

    Also Please ensure with your backend processor is waiting for a low power (LP) to high speed (HS) transition on the MIPI clock lanes on the ADV7280-M. By default the ADV7280-M will only perform a LP -> HS transition once after it has been configured. It will then remain in HS mode.

    *** We were able to probe the initial LP to HS mode transition on MIPI CSI Clock lane. The voltage level at LP and HS modes are matching as per the requirement. Can we assume from this that whether the Back end processor is properly terminating with 50 Ohm and 100 ohm at LP and HS modes respectively by detecting the LP and HS modes. If not, how we will ensure whether the back end processor is detecting this LP to HS mode transition or not?.  Refer the attached image below.

    We can force a LP-> HS transition by setting the CSI Map register 0x00 to the value 0x80 and then back to the value 0x00.

    *** We were able to see LP->HS transition on oscilloscope without forcefully writing 0x80 to CSI Map Register: 0x00

    5)  MIPI Termination:

    You can use the University of New Hampshire MIPI reference termination board.

    For our evaluation of the ADV7280-M We used the MIPI reference termination board which is available from here:
    MIPI Test Boards | InterOperability Laboratory

     When you terminate the output signals from the ADV7280-M (in a micro processor/ FPGA) then you will see the correct MIPI traces. Note that the Micro processor/ FPGA needs to be able to detect the output format (high speed mode or low power mode) and dynamically change its input impedance. If the micro processor/ FPGA does not control the termination correctly then the MIPI signals from the ADV7280-M cannot be decoded.

    ***As mentioned above, we are able to probe LP and HS voltages as 1.2V and 0.1V & 0.3V exactly on both Clock and Data lanes as mentioned in the AN1337. Can we assume from this that whether the Back end processor is properly terminating with 50 Ohm and 100 ohm at LP and HS modes respectively by detecting the LP and HS modes. if not, how we will ensure the same.

    I believe that your MIPI receiver (micro processor/ FPGA) has not been configured correctly.

    *** We are awaiting for the response from Back end processor team (iMX8M) to confirm the MIPI receiver configurations.

    This is described in applications note AN-1337

    http://www.analog.com/media/en/technical-documentation/application-notes/AN-1337.pdf

    Ensure the proper clock rate(27Mhz) has given. All filtering and termination is performed in the D-PHY layer of the ADV7280-M,ADV7281-M, ADV7281-MA, and ADV7282-M transmitter devices and in the D-PHY layer of the MIPI CSI-2 receiver. Do not place additional components, such as resistors, electrostatic discharge (ESD) diodes, capacitors, or common-mode chokes on the MIPI CSI-2 traces.
    Please ensure with good ground connections on the board i. ground plane.

    *** Our understanding is like 27MHz CLK is referring to BYTE clock for D-PHY. Assuming the D-PHY will be part of iMX processor and byte clock will be generated by Back end processor in our case iMX8  (Refer below snippet from iMX8 MII CSI Clock config. section for your quick reference).

    *** Is this 27MHz is the crystal frequency for ADV7280? if yes, then this frequency is 28.636MHz and already shared the waveform in the previous reply. 

     

    *** We observed the MIPI CLK from ADV is 216MHz for progressive mode. Also provided proper ground reference and none of the above components were placed on traces. We also verified the trace impedance and length matching requirement as per the MIPI CSI layout guide lines, Total length of the traces from iMX to ADV 7280 is Approx. 110mm.

    As per expert comment, PVDD is very important for maintaining the video stability.

      Ideally it should be ferrite bead isolated from other supplies and the data sheet reference schematic does not show this which is OK if the PVDD source is very clean. 

      First check PVDD noise both high frequency and lower frequencies around the horizontal rates.  If noise is coupled into PVDD then the PLL might lose lock and causing image issues.

    Also make sure with below things,

    1. First verify the PVDD_1.8V for the ELPF remains stable and clean when the problem shows up.

    *** Verified the voltage level and the voltage is stable and clean. Refer the below attached image

    2. Check that all voltages are clean and stable.

    *** Verified all the power rails of ADV7280 and the voltage is stable and clean within the limits.

    3. Try C0G (NPO) material caps and see if that resolves the issue.

    *** as we are getting all the voltage rails properly, assume no need to replace with C0G (NPO) capacitor.

    Note: In low power mode the termination needed is 50 Ohm single ended. In high speed mode termination needed is 100 Ohm differential. Please refer reference schematic at (+) ADV7281/ADV7281-M / ADV7281-MA Design Support Files - Documents - Video - EngineerZone (analog.com).

    *** Yes, We have matched the impedances in layout as per the requirements of 50 ohms single ended and 100 ohms differential pair. Already compared and verified our schematics with respect to EVK schematics provided by Analog devices. Also understood that different termination for LP and HS mode are to be set by iMX8M inside the chip by detecting the mode of transmission.

    Please refer freescale community at Home - NXP Community.

    *** LP>HS transition on MIPI CSI clock lane during the initialization.

    *** PVDD voltage rail.

    please let us know if any more details are required.

  • Hi Poornima,

    Adding detailed response regarding driver configuration and register settings on above reply. see below,

    *** Driver integrated is from mainline kernel:

     http://git.kernel.org/cgit/linux/kernel/git/torvalds/linux.git/tree/drivers/media/i2c/adv7180.c

     

    Drivers we are using:

    ADV7280M Driver = drivers/media/i2c/adv7180.c

    IMX Capture Driver ( MIPI CSI driver)  = drivers/media/platform/imx8/mxc_mipi_csi.c

    MIPI CSI-2 Driver ( CSI Bridge driver )  = drivers/media/platform/mxc/capture/mx6s_capture.c

     

    PFB Changes we have done in dtsi for MIPI:

    file : arch/arm64/boot/dts/freescale/imx8mm-evk.dtsi

     

            adv7280m: adv7280@21 {

                    compatible = "adi,adv7280-m";

                    reg = <0x21>;

                    pinctrl-names = "default";

                    pinctrl-0 = <&pinctrl_csi_rst>;

                    reset-gpios = <&gpio1 14 GPIO_ACTIVE_LOW>;

                    irq-gpios = <&gpio1 6 GPIO_ACTIVE_LOW>;

                    interupt-parent = <&gpio1>;

                    interrupt = <6 GPIO_ACTIVE_LOW>;

                    adv,force-bt656-4 = <1>;

                    status = "okay";

                    port {

                            adv7280m_out: endpoint {

                                   clock-lanes = <1>;

                                   data-lanes = <1>;

                                   remote-endpoint = <&mipi1_sensor_ep>;

                            };

                    };

            };

     

     

    &mipi_csi_1 {

            #address-cells = <1>;

            #size-cells = <0>;

            status = "okay";

            port {

                    mipi1_sensor_ep: endpoint@1 {

                            remote-endpoint = <&adv7280m_out>;

                            clock-lanes = <1>;

                            data-lanes = <1>;

                            csis-hs-settle = <13>;

                            csis-clk-settle = <2>;

                            csis-wclk;

                            bus-width = <1>;

                    };

     

                    csi1_mipi_ep: endpoint@2 {

                            remote-endpoint = <&csi1_ep>;

                    };

            };

    };

     

    &csi1_bridge {

            fsl,mipi-mode;

            status = "okay";

            port {

                    csi1_ep: endpoint {

                            remote-endpoint = <&csi1_mipi_ep>;

                    };

            };

    };

     

    IMX8MM MIPI CSI Reg Dump:

    MIPI_CSI_CSIS_COMMON_CTRL: 0x00004005

    MIPI_CSI_CSIS_CLOCK_CTRL: 0x000f0000

    MIPI_CSI_INTERRUPT_MASK_0: 0xf00fffff

    MIPI_CSI_INTERRUPT_MASK_1: 0x00000000

    MIPI_CSI_DPHY_STATUS: 0x000000e1

    MIPI_CSI_DPHY_COMMON_CTRL: 0x0d800003

    MIPI_CSI_DPHY_SLAVE_CTRL_LOW: 0x0000000

    MIPI_CSI_DPHY_SLAVE_CTRL_HIGH: 0x000000

    MIPI_CSI_ISP_CONFIG_CH0: 0x00000078

    MIPI_CSI_ISP_RESOLUTION_CH0: 0x01e002d0

    Awaiting for your response.

     

  • Hi,

      Please find the below comments,

     If not, how we will ensure whether the back end processor is detecting this LP to HS mode transition or not?

      The LP to HS mode transition on the MIPI CSI-2 clock lane occurs only once on the ADV728x-M, ADV728x-MA immediately after they are initially programmed.

      MIPI CSI-2 receivers wait for an LP to HS mode transition on the MIPI CSI-2 clock lane before starting video capture.

      If the MIPI CSI-2 receiver is initialized after the transmitter device is initialized, the MIPI CSI-2 may never detect the LP to HS mode transition on the clock lane from the transmitter device. If the MIPI CSI-2 receiver does not detect the LP to HS mode transition, it may never start video capture.

    Note : To manually program the clock lane of the ADV728x-M,ADV728x-MA, or ADV7282-M to enter and then exit LP mode.The easiest way to do this is by toggling the CSITX_PWRDN bit (Address 0x00, Bit 7).The MIPI CSI-2 receiver then recognizes an LP to HS mode transition and begins video capture.

    Thanks,

    Poornima

  • Hi Poornima,

    Thank you for the reply.

    As recommended in your previous post, we forcefully toggled the LS -> HS state in the adv7180.c just before starting the stream.

    --- a/drivers/media/i2c/adv7180.c
    +++ b/drivers/media/i2c/adv7180.c
    @@ -940,6 +940,8 @@ static int adv7180_s_stream(struct v4l2_subdev *sd, int enable)
            int ret;
     
             pr_err("%s: Enter\n",__func__);
    +       adv7180_csi_write(state, 0x00, 0x80);
    +       adv7180_csi_write(state, 0x00, 0x00);
            /* It's always safe to stop streaming, no need to take the lock */
            if (!enable) {

    we successfully able to see the test pattern.

    can you please confirm if the colors on the color bar test pattern are right

    Thank you again Slight smile

  • Hi,

     Please compare your test pattern with MIPI packet output from the ADV7280-M in free-run mode using a Keysight U4421A MIPI protocol analyzer.

     The captured MIPI packets are available at "1258.ADV728xMIPIfreerun.zip" - ADV7280-M design support files .

    Thanks,

    Poornima

  • Hi Poornima,

    It seems the colours are not right, Can you please guide on correcting the same.

    We already tried to swap the Cb and Cr bits but we still are getting the same output.

    Also there is a green bar on the top and left side of the preview. We are currently running adv7280M in NTSC BT656-3 Mode and 720x507 resolution.

    We can also see strips on the image even though the I2P core is enabled.

    Regards,

    T

  • Hi,

      Please make sure the crystal frequency as '28.636MHz' ( Whether the crystal is really 28.636MHz, not 27MHz -  28.636 on the XTAL_IN pin ).

    By default the ADV728x video decoders receive analog video and output digital video in accordance with the ITU-R BT.656-3 standard.
    If the receiver system is expecting an ITU-R BT.656-4 output from the ADV728x then this can result in 10 lines of extra video being output at the top of the screen.

    Please ensure the below SWAP register,

    Swap Pixel Cr/Cb, Address 0x27[7] This bit allows Cr and Cb output samples to be swapped. This bit affects ADV728x-T and ADV728x-M models.
    When SWPC is 0 (default), no swapping is allowed. When SWPC is 1, the Cr and Cb output values are swapped.

    Thanks,

    Poornima