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[ADV7619] I2C SDA was pulled to low under certain probability, while system was repowering on and ADV7619 was being accessed by I2C.

Category: Software
Product Number: ADV7619
  1. 1. ADV7619 on the board is to tranfer 4K30 HDMI to VP.

  2. 2. The probability of the fault is about 1%,  1 time fault of 100 times powering on.

  3. 3. The wave of every fault is same,and is as below:

  4. The waves of the last four access to ADV7619 is zoomed as below:

  5. DPLL Map(the I2C address is 0xAC), writing 0x80 to Register 0xC3

  6. DPLL Map(the I2C address is 0xAC), writing 0x03 to Register 0xCF

  7. IO Map(the I2C address is 0x98), writing  0x00 to Register 0xDD

  8. IO Map (the I2C address is 0x98), writing the register address of 0xE6,and SDA was pulled low



Changed ADV7916 to ADV7619
[edited by: mattp at 10:48 PM (GMT -4) on 1 Aug 2022]
  • What script files are you following.  I cannot find any script file or data sheet entry listing 0x98 0xE6

  • I think the last register is 0xE7, the level of the last bit is lower than other 0 level from the master, but higher than the ACK's level. This is abnormal, and some error has happened at this bit I think.

  • The host is puling SDA to it's low level and the ADV7619 is pulling SDA to a lower level.  This is not uncommon.  It all depends on how the open collector circuits are implemented.

  • Maybe the host was pulling SDA to high level, and at the same time the ADV7619 was pulling it to low level, so the level was higher than ACK. If they both pulled it low, I think the level would be the same as the ACK's.

  • We have some questions:

    1. When will the ADV7619 request the host to set do the following steps?

    set DPLL Map 0xC3 to 0x80; set DPLL Map 0xCF to 0x03;IO Map 0xDD to 0x00; and set IO Map 0xE7 to some value.

    2. So far, the fault always happenned at the system repowering up, does ADV7619 have any special requirements after powered up?

  • The code of setting IO Map 0xDD to 0x00 and IO Map 0xE7 to 0x04 was changed in march 2020. That is to sovle the problem of clock phase shifted. The solution is discribed in "ADV7619_Clock_Path_Fix.pdf", which was provided by ADI on march 23th 2020.

  • A) The fact that the SDA line only goes to the lowest level during the ADV7619 ACK period and the rest of the time the SDA line is toggling indicates the ADV7619 is not pulling the SDA line low during non ACK periods.

    B) What script files are you getting your setting from.  You should be using the scripts from

    2) The power up sequence should be as shown in the data sheet.  The key is that the 1.8V rail should not exceed the 3.3V rail during the power up cycle.  Reset should be held low ~5ms after the rails become stable.

    Unfortunately I can't track down "ADV7619_Clock_Path_Fix.pdf".  Can you attach it here so I can see it's source.  Not sure what it says.

  • Thank you for reply.

    1)  Please help checking the power up sequence.

    ADV7619 power sequence(yellow wave is 3.3V,blue wave is 1.8V)

    ADV7619 1.8V power up(yellow, which was in power cycle) and reset signal(blue)

    ADV7619 the second reset pulse is zoomed as below(blue, held about 50 ms)

    2) ADV769's initialization is done after the second reset, the 4K setting code is as below. Please help check.

    void hdmi_4k_set(int id,UINT8 hdmi_cspace)
        //change the 7619 map address to new address
        ATV_i2c_1_wr_8_8(id, 0x98, 0xF4, 0xAA);
        ATV_i2c_1_wr_8_8(id, 0x98, 0xF5, 0xA8);
        ATV_i2c_1_wr_8_8(id, 0x98, 0xF8, 0xAC);
        ATV_i2c_1_wr_8_8(id, 0x98, 0xF9, 0xA4);
        ATV_i2c_1_wr_8_8(id, 0x98, 0xFA, 0xA6);
        ATV_i2c_1_wr_8_8(id, 0x98, 0xFB, 0xA2);
        ATV_i2c_1_wr_8_8(id, 0x98, 0xFD, 0xAE);//meijd modified cp map to 0x57
        ATV_i2c_1_wr_8_8(id, 0xA2, 0xC0, 0x03);
        ATV_i2c_1_wr_8_8(id, 0x98, 0x01, 0x05);//meijd modified for 4k doudong 20200324
        ATV_i2c_1_wr_8_8(id, 0x98, 0x00, 0x19);//meijd modified for 4k doudong 20200324
        ATV_i2c_1_wr_8_8(id, 0x98, 0x02, 0xF2);
        ATV_i2c_1_wr_8_8(id, 0x98, 0x05, 0x28);
        //ATV_i2c_1_wr_8_8(id, 0x98, 0x06, 0xA0);//meijd add for outputsync
        ATV_i2c_1_wr_8_8(id, 0x98, 0x06, 0xA0);//meijd add for outputsync
        ATV_i2c_1_wr_8_8(id, 0x98, 0x0C, 0x42);
        //ATV_i2c_1_wr_8_8(id, 0x98, 0x15, 0x80);
        ATV_i2c_1_wr_8_8(id, 0x98, 0x15, 0x80);//meijd add for outputsync
        ATV_i2c_1_wr_8_8(id, 0x98, 0x19, 0x80);//meijd modified for 4K shake, disable the DLL ,change form 0X83->0x00
        ATV_i2c_1_wr_8_8(id, 0x98, 0x33, 0x40);//meijd modified for 4K shake, disable the DLL ,change form 0X83->0x00
        ATV_i2c_1_wr_8_8(id, 0xAC, 0xB5, 0x01);
        ATV_i2c_1_wr_8_8(id, 0xAC, 0xC3, 0x80);
        ATV_i2c_1_wr_8_8(id, 0xAC, 0xCF, 0x03);
        ATV_i2c_1_wr_8_8(id, 0x98, 0xDD, 0x00);//meijd modified for 4k doudong 20200324
        ATV_i2c_1_wr_8_8(id, 0x98, 0xE7, 0x04);//meijd modified for 4k doudong 20200324
        ATV_i2c_1_wr_8_8(id, 0x98, 0xBF, 0x00);
        ATV_i2c_1_wr_8_8(id, 0xA2, 0xC0, 0x03);
        ATV_i2c_1_wr_8_8(id, 0xA2, 0x00, 0x08);
        ATV_i2c_1_wr_8_8(id, 0xA2, 0x02, 0x03);
        ATV_i2c_1_wr_8_8(id, 0xA2, 0x03, 0x98);
        ATV_i2c_1_wr_8_8(id, 0xA2, 0x10, 0xA5);
        ATV_i2c_1_wr_8_8(id, 0xA2, 0x1B, 0x00);
        ATV_i2c_1_wr_8_8(id, 0xA2, 0x45, 0x04);
        ATV_i2c_1_wr_8_8(id, 0xA2, 0x97, 0xC0);
        ATV_i2c_1_wr_8_8(id, 0xA2, 0x3E, 0x69);
        ATV_i2c_1_wr_8_8(id, 0xA2, 0x3F, 0x46);
        ATV_i2c_1_wr_8_8(id, 0xA2, 0x4E, 0xFE);
        ATV_i2c_1_wr_8_8(id, 0xA2, 0x4F, 0x08);
        ATV_i2c_1_wr_8_8(id, 0xA2, 0x50, 0x00);
        ATV_i2c_1_wr_8_8(id, 0xA2, 0x57, 0xA3);
        ATV_i2c_1_wr_8_8(id, 0xA2, 0x58, 0x07);
        ATV_i2c_1_wr_8_8(id, 0xA2, 0x6F, 0x08);
        ATV_i2c_1_wr_8_8(id, 0xA2, 0x83, 0xFC);
        ATV_i2c_1_wr_8_8(id, 0xA2, 0x84, 0x03);
        ATV_i2c_1_wr_8_8(id, 0xA2, 0x85, 0x10);
        ATV_i2c_1_wr_8_8(id, 0xA2, 0x86, 0x9B);
        ATV_i2c_1_wr_8_8(id, 0xA2, 0x89, 0x03);
        ATV_i2c_1_wr_8_8(id, 0xA2, 0x9B, 0x03);
        ATV_i2c_1_wr_8_8(id, 0xA2, 0x93, 0x03);
        ATV_i2c_1_wr_8_8(id, 0xA2, 0x5A, 0x80);
        ATV_i2c_1_wr_8_8(id, 0xA2, 0x9C, 0x80);
        ATV_i2c_1_wr_8_8(id, 0xA2, 0x9C, 0xC0);
        ATV_i2c_1_wr_8_8(id, 0xA2, 0x9C, 0x00);
    		case 0:
    		case 2:
    			ATV_i2c_1_wr_8_8(id, 0x98, 0x03, 0x54);
    		case 1:
    			ATV_i2c_1_wr_8_8(id, 0x98, 0x03, 0x94);

    3)"ADV7619_Clock_Path_Fix.pdf" is as below.


    4)Can you explain the function of the following setting discribed in the scripts “ADV7619-VER.1.9c“? Upnow, we haven't done that.

    ; ---------------------------------------------------------------------
    ; Version 1.9c
    ; Added write to DPLL map for modes > 170MHz
    ; For modes > 170MHz, added write 4C DB 80 ; ADI Required Write
    ; ---------------------------------------------------------------------

  • When the fault happened, short the reset pin of ADV7619 to GND, and then release it, the I2C will recover.

    If short the SCL to GND, and then release it, the SDA will go high, but there still is no wave on I2C lines.