It would be greatly helpful if you provide some basic VHDL/Verilog code for testing the EVK ADV739x.
Kindly do needful so that I can progress my work soon.
Thanks in advance.
Please find the below VHDL code link & It has been worked great with one of the ADV7391 customer.
Customer used config script in Table 82 of the ADV datasheet, and had to make very small changes to the code provided by spacewire to make it work (pal config and remove clock inversion)