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ADV7181C 525i Video Rolling Problem

Category: Software
Product Number: ADV7181CWBSTZ


We source a STANAG3350C video format to ADV7181C with SoG RGB signals. Then we output the digital signals 4:2:2 525i 16bit CP to the IMX6 CSI0 port.

When we start to record a video, the video is rolling up always. I have attached the video file.

If we make any changes to the FR_LL register(0x8F and 0x90), the speed of rolling may increase or decrease. VS_START or VS_END register (0x7E) does not change the rolling speed. We did try most of the registers to fit the screen constant however we couldn't figure out the problem and need your help.

We got help from the document you supplied "Configuring the ADV7181C for RGB with external CSync from a camera"

I attach the registers and the values we use.

42 05 00 ; Prim_Mode =000b for SD-M
42 06 0E ; VID_STD=1110b for SD 2x1 525i
42 1D 47 ; Enable 28MHz Crystal
42 3A 11 ; Set Latch Clock 01b, Power Down ADC3
42 3B 81 ; Enable internal Bias
42 3C 52 ; PLL_QPUMP to 010b
42 52 00 ; Colour Space Conversion from RGB->YCrCb
42 53 00 ; CSC
42 54 12 ; CSC
42 55 90 ; CSC
42 56 38 ; CSC
42 57 69 ; CSC
42 58 48 ; CSC
42 59 08 ; CSC
42 5A 00 ; CSC
42 5B 75 ; CSC
42 5C 21 ; CSC
42 5D 00 ; CSC
42 5E 1A ; CSC
42 5F B8 ; CSC
42 60 08 ; CSC
42 61 00 ; CSC
42 62 20 ; CSC
42 63 03 ; CSC
42 64 D7 ; CSC
42 65 19 ; CSC
42 66 48 ; CSC last
42 67 13 ; DPP Filters
42 6B C3 ; Select 422 16 bit YPrPb out from CP
42 73 0F ; Enable Manual Gain and set CH_A gain
42 74 A3 ; Set CH_A and CH_B Gain - 0FAh
42 75 E8 ; Set CH_B and CH_C Gain
42 76 FA ; Set CH_C Gain
42 7B 06 ; ****clears the bits CP_DUP_AV and AV_Blank_EN****
42 7F 00 ; ****END_VS ends 2 lines early****
42 85 1C ; Turn off SSPD and force SOY. For Eval Board.
42 86 1B ; Enable stdi_line_count_mode
42 8A 50 ; Manual VCO_RANGE=00
42 8F 77 ; FR_LL to 1820 & Enable 28.63MHz LLC
42 90 1C ; FR_LL to 1820
42 BF 06 ; Blue Screen Free Run Colour
42 C0 F0 ; default color
42 C1 00 ; default color
42 C2 F0 ; Default color
42 C5 01 ; CP_CLAMP_AVG_FACTOR[1-0] = 00b
42 C9 0C ; Enable DDR Mode
42 F3 07 ; Enable Anti Alias Filters on ADC 0,1,2
42 0E 80 ; ADI Recommended Setting
42 52 46 ; ADI Recommended Setting
42 54 00 ; ADI Recommended Setting
42 F6 3B ; ADI Recommended Setting
42 0E 00 ; ADI Recommended Setting

Thanks in advance.

  • Hi,

       Please let us know, whether you are not facing this video rolling problem issue with other general format other than STANAG input.

       Also please ensure with below things,

      --> Make sure the vertical output pin is stable & frequency, pulse width.

      --> Then check the vertical output pin have the correct amplitude and sharp edges

      --> Check if the chip power supplies are clean and well decoupled.  Make sure there is no noise getting injected into the ADC section of the chip. Scope the analog signals looking for this noise.



  • Hi, thanks for your reply.

    Actually, as you can see in my previous post, I did not connect the video source to the decoder. It runs in FREE RUN mode. When I connect the source, it is also rolling.

    • Do you mean VS(Vertical Sync) pin with vertical output pin?
    • What is the correct amplitude of the VS pin? Is it 3.3V digital signal?
    • I have checked with a scope and there is no problem with power supply or decoupled capacitors or noise.


  • Hi,

      By using freerun feature, We can validate the part and also it provide the stable clock when there is no input connected.

      Please let us know, even in SDP core its not possible for you to generate the free run ?

           42 0C 37 ; Force Free run mode in SDP [Free run]



  • Thanks for your reply.

    However, 0C 37 setting did not work. 

    We can validate the part and also it provide the stable clock when there is no input connected.

    I think we have a stable clock issue as you mentioned. 

    What are the appropriate values for the FR_LL register in 525i format?

    By the way, did you check the register values in my first post?

  • Hi,

    By the way, did you check the register values in my first post ?

       Yes, Above "FR_LL" register configuration for 525i format seems correct.

        To calculate the FR_LL[10:0] manual parameter, the line period is divided by the 28 MHz clock period (As per below equation). The numerator in this equation can be calculated directly from the Hysnc period, or by using the total number of luma pixel periods per line multiplied by the pixel clock period.

           FR_LL = Tline/T28.63 Mhz.

    Please check this document for "FR_LL" register programming /cfs-file/__key/communityserver-discussions-components-files/331/Nonstandard_5F00_Video_5F00_Formats_5F00_17_5F00_Sept_5F00_08.pdf

    Free run should work, Just for debug purpose Could you please try configuring the FR_LL(0x8F) register to zero, so that  internally used free-run line length value is decoded from the current setting of PRIM_MODE and VID_STD.

    Note:  Generally FR_LL is used for free rum mode configuration.The CP uses the line length measurement to decide when to go into free-run state. And also CP uses VID_STD to determine the expected line length.
    To configure the CP for nonstandard video, the FR_LL[11:0] must be set manually. CP must be manually programmed to expect a different line length for non standard formats.
    To calculate the FR_LL[11:0] manual parameter, the line period is divided by the 27 MHz clock.