Post Go back to editing

AD9984A_DATACK at 59.94Hz signals.

Category: Datasheet/Specs
Product Number: AD9984A

Dear Sir

We study AD9984A now.

We have the question of AD9984 at 59.94Hz signal as follows.


Resolution:  1080p59.94Hz(DotCLK=148.35MHz)/1080i59.94Hz(DotCLK=74.175MHz)/720p59.94Hz(DotCLK=74.175MHz)

Can AD9984A support  to generate DotCLK of these resolution without External Clock(EXTCK)?

We refer design support files docmentation,"0830.attachment.xls".

 AD9984A / AD9983A Design Support Files - Documents - Video - EngineerZone (

As "0830.attachment.xls" , it seems that AD9984A can support  59.94Hz signals.

F column is "Sampling Frequency (MHz)" .

Does "Sampling Frequency (MHz)"  means that it equal to output  "DATACK"?

59.94Hz signal is detailed clock.

We are concerned whetehr AD9984A can generate 59.94Hz without EXTCK  .

BR Isshin kida 

  • Hi Isshinkida San,

          Please find the below comments,

           Can AD9984A support  to generate DotCLK of these resolution without External Clock(EXTCK) ?

    Please refer "0x03—Bit[2] External Clock Enable" register.

    External Clock Enable
     0 Internally generated clock.
     1 Externally provided clock signal.
    A Logic 0 enables the internal PLL that generates the pixel clock from an externally provided Hsync.
    A Logic 1 enables the external EXTCK input pin. In this mode, the PLL divide ratio (PLLDIV) is ignored. The clock phase adjust (Phase) is still functional. The power-up default value is EXTCK = 0.


       EXTCK allows the insertion of an external clock source rather than the internally generated, PLL locked clock. EXTCK is enabled by programming Register 0x03

    When .... EXTCK function are not used, this pin can be grounded and coast polarity programmed to 1. Input coast polarity defaults to 1 at power-up. This COAST function does not affect the EXTCK function.

    Does "Sampling Frequency (MHz)"  means that it equal to output  "DATACK" ?

       Yes,it is equal to DATACK.

        Sample clock output frequencies range from 10 MHz to 170 MHz.



  • Dear Poornima-san

    Thank you for your reply.

    As your reply,is my understanding that AD9984A can support DATACK at 148.35MHz and 74.175MHz without EXTCK function(EXTCK = 0)  for 59.94Hz signals,correct?

    BR Isshin kida

  • Hi Isshinkida San,

             Yes You can.

    Please note PLL multiplies the frequency of the Hsync signal, producing pixel clock frequencies in the range of 10MHz to 170MHz
        PLL is used to generate the pixel clock. The Hsync input provides a reference frequency to the PLL ( DATACK is generate from H sync using the internal PLL.  There's no need for an external clock ).



  • Dear Poornima-san,

    Thank you for your reply.

    We understood internal PLL an External clock function.


    Isshin kida