Internal Test Pattern ADV7393 with ATV Benchtop

Hi,

  Please ensure, whether you are supplying the 27MHz clock.

  The CLKIN is required for the color bar Since the part can't generate the clock on it's own.

Thanks,

Poornima

Hi,

I seeing to signal waveform same as page 89 of the ADV7393 datasheet .

But my signal peak to peak voltage 200mV. For display I used to 3.5 inç TFT monitor.

This monitor resolution 320x234. When I connect to DAC1 out to monitor I seeing peak to peak voltage drop to 100mV.

What path should I follow in order to observe the DAC output correctly?

Best Regard.

Hi,

I seeing to signal waveform same as page 89 of the ADV7393 datasheet .

But my signal peak to peak voltage 200mV. For display I used to 3.5 inç TFT monitor.

This monitor resolution 320x234. When I connect to DAC1 out to monitor I seeing peak to peak voltage drop to 100mV.

What path should I follow in order to observe the DAC output correctly?

Best Regard.

Hi,

  Please ensure with below things on ADV739x part and also share your register configuration,

    ADV7391 DAC output current is proportional to Rset and Rload.DAC is a current output based on digital input values, Rset and Rload.  If you increase Rload by 20% the effective output voltage would increase by 20% with the caveat that the output voltage does not exceed 1.4V.  We do not test this or specify these limits beyond what is defined in the data sheet.

  ADV739x contains an RSET pin. A resistor connected between the RSET pin and AGND is used to control the full-scale output current and, therefore, the output voltage levels of DAC 1, DAC 2, and DAC 3. For fulldrive operation, RSET must have a value of 510 Ω and RL must have a value of 37.5 Ω. For low drive operation, RSET must have a value of 4.12 kΩ, and RL must have a value of 300 Ω. The resistor connected to the RSET pin should have a 1% tolerance.

  Note: When Rset = 510 Ohms, the DAC outputs expect to see a 37.5 Ohm load.  The load consists of a 75 Ohm resistor to ground right next to the pin and a 75 Ohm resistor to ground at the sink.  Normal cables plus sinks are set up this way.

           The encoders expect to be terminated with 75 ohms on your PCB with another 75 ohms at the end of the transmission line, so the total load resistance is 37.5 Ohms.

Thanks,

Poornima

Hi,

0x00 --> 1C
0x13 --> 34
0x16 --> 57
0x33 --> 40
0x39 --> 02
0x82 --> C3
0x84 --> 40
0x8C --> 1F
0x8D --> 7C
0x8E --> F0
0x8F --> 21
0xBB --> 78

You can see above register address and values of  EVAL-ADV7393EBZ. All other values are 0 include ADV739XFEZ FPGA register space.

As I said before I used to EVAL-ADV7393EBZ and EVAL-ADV739XFEZ. In this board Rset = 510 Ohms and RLoad 75 Ohm. I have no idea about end of transmission line. I don't have any information about display monitor.

Best Regard.

Hi,

  Please again ensure whether you are applying 27MHZ signal to ADV739x CLKIN pin since the default frequency from FPGA is 28Mhz.

  Please try with below settings and let us know the result.

NTSC:

PAL:

Thanks,

Poornima

Hi,

0x00 --> 00
0x13 --> 00
0x16 --> 1E
0x33 --> 01
0x39 --> 02

Above registers settings belongs to xilinx spartan-3. I used to 27Mhz clock from osc. I saw this clock properly on the oscilloscope and CLKIN pin of the ADV7393.

I changed to 0x82 with CB . Now I seeing to waveform of colour bar peak-to-peak voltage 1V.

Thanks.

Hi,

  Could you please check with other Monitor or TV ?

  Since you are observing the color bar waveform thtsy.

Thanks,

Poornima