ADV7341 application problems 1

Hi,

  Could you please share your register configuration and we want to check your format & I2C related configuration ?

Thanks,

Poornima

SD
CVBS
I2C：
ADDR1 = 8'h17,DATA1 = 8'h02,//reset
ADDR2 = 8'h00,DATA2 = 8'hFC,
ADDR3 = 8'h80,DATA3 = 8'h11,
ADDR4 = 8'h82,DATA4 = 8'hCB,
ADDR5 = 8'h84,DATA5 = 8'h40,
ADDR6 = 8'h8C,DATA6 = 8'hCB,
ADDR7 = 8'h8D,DATA7 = 8'h8A,
ADDR8 = 8'h8E,DATA8 = 8'h09,
ADDR9 = 8'h8F,DATA9 = 8'h2A;

Hi,

  Please let us know, whether you are generating color bar ? If you are generating color bar then it is not possible to get -300mv

   To get -300mV, Refer section "COPY GENERATION MANAGEMENT SYSTEM" for register configuration.

  Please note "If you want to enable the CGMS data, enable the VBI bit and the CGMS enable bit".

Thanks,

Poornima

Figure 124 in the manual shows the level of RGB output. The low level is 0mV, but the lowest level of CVBS output should be the level of synchronization signal, which is -300mv. The level of the synchronization signal we see with the oscilloscope is 0mV. Why

Hi,

  Please let us know your source device and also your input format.

  If possible, kindly share your connection setup.

Thanks,

Poornima

设计的原理图如下：

Using the chip self-test mode, there is no source device

Hi,

 As stated earlier in previous post, If you are in chip self-test mode (i.e Internal test pattern) then it is not possible for -300mV .

Thanks,

Poornima

The purpose of the test mode should be to output video test without a source. Why can't the lowest level be -300mv when testing output?

Hi,

Why can't the lowest level be -300mv when testing output ?

  As per specification, for test pattern the lowest level is 0mV only.

  But this need to be check with expert about why -300mV is not possible for internal test pattern.

  Please let us know, Have you tried with CGMS type input by enabling below register ?

Thanks,

Poornima

0x32 register configuration is 0x00

Hi,

  Please configure the 0x32(ED/HD CGMS) register as 0x40 (Enabling 6th bit to 1) and let us know the result.

Note: ADV7343 support a copy generation management system (CGMS) in 625p mode in accordance with IEC62375 (2004).
When ED CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 625p CGMS data is inserted on Line 43. 625p CGMS data registers are at Subaddress 0x42 and Subaddress 0x43.

Please refer Page no: 76 in ADV734x datasheet for different mode of CGMS mode.

Thanks,

Poornima

Hi,

  Please configure the 0x32(ED/HD CGMS) register as 0x40 (Enabling 6th bit to 1) and let us know the result.

Note: ADV7343 support a copy generation management system (CGMS) in 625p mode in accordance with IEC62375 (2004).
When ED CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 625p CGMS data is inserted on Line 43. 625p CGMS data registers are at Subaddress 0x42 and Subaddress 0x43.

Please refer Page no: 76 in ADV734x datasheet for different mode of CGMS mode.

Thanks,

Poornima