ADV7341 application problems 1

Hi,

  Could you please share your register configuration and we want to check your format & I2C related configuration ?

Thanks,

Poornima

SD
CVBS
I2C：
ADDR1 = 8'h17,DATA1 = 8'h02,//reset
ADDR2 = 8'h00,DATA2 = 8'hFC,
ADDR3 = 8'h80,DATA3 = 8'h11,
ADDR4 = 8'h82,DATA4 = 8'hCB,
ADDR5 = 8'h84,DATA5 = 8'h40,
ADDR6 = 8'h8C,DATA6 = 8'hCB,
ADDR7 = 8'h8D,DATA7 = 8'h8A,
ADDR8 = 8'h8E,DATA8 = 8'h09,
ADDR9 = 8'h8F,DATA9 = 8'h2A;

Hi,

   If is an PAL test pattern, Please make sure with below register settings,

     0x17  - 0x02

    0x00 - 0xFC

    0x82 - 0xC9  // Your configuration is different

    0x84 - 0x40

    0x80 - 0x11

    0x8C - 0xCB

    0x8D - 0x8A

    0x8E - 0x09

    0x8F - 0x2A

If it is an NTSC color test pattern, Please make sure with below register settings,

    0x17  - 0x02

    0x00 - 0xFC

    0x82 - 0xC9

Please note as per specification for SD pattern(Page 82), CVBS output is available on DAC 4, S-Video (Y-C) output is on DAC 5 and DAC 6, and YPrPb output is on DAC 1 to DAC 3. So you should configure 0x82 register as 0xC9 but you have configured it as 0xCB. Please refer Table37 in ADV734x datasheet.

Thanks,

poornima.S

Configure and adjust the circuit according to the idea you provided, but the lowest level of the output waveform is still not reduced from 0mV to -300mv. Why?

Hi,

 Please ensure your schematic with reference one which is available at  3021.ADV734x_Evaluation_Board_Documents.zip

 DAC output current is proportional to Rset and Rload.  Full drive mode is defined as 34.7mA with 37.5 Ohm load and 0xFF digital inputs giving an output of 1.3V.  Using the +7.5% gain would be 1.4. Please refer "DAC CONFIGURATIONS" section.

 Also note, when the internal color bars test pattern is enabled. The test pattern is not a standard 75% or 100% color bar test pattern, but some customers have used these color bars as a test pattern to test their system design. Please refer this FAQ about   ADV739X Internal Color Bars Output Levels

Thanks,

Poornima

After checking the schematic diagram, it is consistent with the 3021 design, but the lowest level voltage is 0mV instead of -300mv. Is there any other way to adjust it?

Hi,

 Please let us know, whether you are using CGMS type input ?

 We are seeing -300mV only for CGMS type of input in the specification.

Thanks,

Poornima

Hi,

   As per your above shared configuration is seems like color bar related one, If so the voltage will start only from 0mV. Please refer below snap& also datasheet at Page90 - SD/ED/HD RGB OUTPUT LEVELS.

Thanks,

Poornima

Hi,

  Please let us know, whether you are generating color bar ? If you are generating color bar then it is not possible to get -300mv

   To get -300mV, Refer section "COPY GENERATION MANAGEMENT SYSTEM" for register configuration.

  Please note "If you want to enable the CGMS data, enable the VBI bit and the CGMS enable bit".

Thanks,

Poornima

Hi,

  Please let us know, whether you are generating color bar ? If you are generating color bar then it is not possible to get -300mv

   To get -300mV, Refer section "COPY GENERATION MANAGEMENT SYSTEM" for register configuration.

  Please note "If you want to enable the CGMS data, enable the VBI bit and the CGMS enable bit".

Thanks,

Poornima

Figure 124 in the manual shows the level of RGB output. The low level is 0mV, but the lowest level of CVBS output should be the level of synchronization signal, which is -300mv. The level of the synchronization signal we see with the oscilloscope is 0mV. Why

Hi,

  Please let us know your source device and also your input format.

  If possible, kindly share your connection setup.

Thanks,

Poornima

设计的原理图如下：

Using the chip self-test mode, there is no source device

Hi,

 As stated earlier in previous post, If you are in chip self-test mode (i.e Internal test pattern) then it is not possible for -300mV .

Thanks,

Poornima

The purpose of the test mode should be to output video test without a source. Why can't the lowest level be -300mv when testing output?

Hi,

Why can't the lowest level be -300mv when testing output ?

  As per specification, for test pattern the lowest level is 0mV only.

  But this need to be check with expert about why -300mV is not possible for internal test pattern.

  Please let us know, Have you tried with CGMS type input by enabling below register ?

Thanks,

Poornima

0x32 register configuration is 0x00

Hi,

  Please configure the 0x32(ED/HD CGMS) register as 0x40 (Enabling 6th bit to 1) and let us know the result.

Note: ADV7343 support a copy generation management system (CGMS) in 625p mode in accordance with IEC62375 (2004).
When ED CGMS is enabled (Subaddress 0x32, Bit 6 = 1), 625p CGMS data is inserted on Line 43. 625p CGMS data registers are at Subaddress 0x42 and Subaddress 0x43.

Please refer Page no: 76 in ADV734x datasheet for different mode of CGMS mode.

Thanks,

Poornima