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Supplying power to EVAL-ADV7393 from a ZCU102 (over FMC)

Category: Hardware
Product Number: ADV7393

I have the EVAL-ADV7393 eval board, and I need to provide the inputs to the EVAL-ADV7393 from a Xilinx ZCU102 development board via 1 of the 2 HPC FMC connectors.  The inputs to the EVAL-ADV7393 eval board are provided over P1, whose pinout is shown below (taken from the EVAL-ADV7393 schematic):

The 24 digital I/O signals (e.g. SFL, ALSB, I2C Bus, HSYNC, VSYNC, P[0:15], RESET#, CLKIN) are pretty straightforward.  But I need help figuring out how to provide the four power supplies to the ADV7393:

Note that the 24 digital I/O signals will be 1.8V since the ZCU102 HPC FMC signals come from ZYNQ Programmable Logic I/O banks with a maximum voltage level of 1.8V.  So the VDD_IO input to the ADV7393 needs to be 1.8V.

My thought was to tie VAA to +3.3V that comes over the HPC FMC connector and tie the other three power supply inputs to the ADV7393 (i.e. VDD, VDD_IO, and PVDD) to +VADJ that comes over the HPC FMC connector.  (And of course, I would set +VADJ on the ZCU102 to +1.8V.)

According to the VITA 57.1 Specification, the +3.3V lines can carry up to 3 Amps and the +VADJ lines can carry up to 4 Amps, so I don't think there is any issue here.  My main concern is that the ADV7393 Datasheet recommends each of the four power supplies to be provided by a separate regulated supply:

Would there be any issues tying VDD, VDD_IO, and PVDD to the same +VADJ power rail from the ZCU102?

  • The recommended separate power supplies comes from the requirement the PVDD must be very clean followed by VAA.  If you tied PVDD and VDDIO together then any noise on VDDIO will couple back into the PVDD rail which will cause problems.

    Is there anyway you can supply the 7.5V to get power domains working well.  5V would also probably work on this board.

  • Thanks for the quick response and explanation/need for the separate power supplies.  However, I don't understand your suggestions.

    The ADV7393 Datasheet shows all power supply inputs (VDD, VDD_IO, PVDD, and VAA) have max voltage of 1.8V or 3.3V.  Where do you see 7.5V or 5V?

    In your last sentence, what board are you referring to when you say "this board"?

  • Oh, I see, you're talking about the front-end board (i.e. EVAL-ADV739xFEZ), which receives a 7.5V.  I'm not using this board.

    I think you misread my original thread.  I'm talking about how to supply the 4 power supplies to the back-end board (EVAL-ADV7393) from a Xilinx ZCU102 eval board with an FMC daughtercard.  There is no EVAL-ADV739xFEZ in my setup.

  • OK that make more sense now.  The real issue is PVDD must be very clean.  If it is connected to VDDIO coming from the FPGA board, how noisy will it be?  Even though there are inline inductors for the power rails you are going to have more noise then from  linear regulator.  Separate regulators is a recommendation but you can always try connecting like you want to.  

    As long as all the rails come up together there be no power up sequencing issues

  • Okay, thanks for the clarification.  Sounds like for PVDD, being on its own separate linear regulator is the way to go.  Are there are any similar issues (i.e. noise coupling) with tying VDD and VDD_IO together?

  • Just to keep PVDD clean you can use a single 3.3V->1.8V regulator just for that rail.  There's lots of them out there in sot-23 packages or smaller besides the ones used on the reference schematics.

    Tying VDD and VDDIO together are generally is not an issue.  Just use good decoupling configuration with a solid ground plane and noise should be limited.

  • Upon closer look at the Xilinx ZCU102 eval board and our FMC board, there is unfortunately only one +3.3V and +1.8V rail.  And these are both COTS boards that we have purchased, so we can't easily add regulators without doing some rework to them (which I'd strongly like to avoid).

    Another possibility that you mentioned earlier is to use the EVAL-ADV739xFEZ front-end board to provide power to the EVAL-ADV7393 back-end board.  Can I ask a few questions about this possibility:

    1. Does this mean I would have to connect the ZCU102 to the Expansion Port (J4) on the EVAL-ADV7393xFEZ?

    2a. On page 6 of the EVAL-ADV739xFEZ schematic, there is a note for "FPGA-VAR3V3" that says it applies to FPGA I/O banks 0,1,2,3.  What specific pin numbers on the FPGA do I/O banks 0,1,2,3 pertain to?  (I tried to look it up in the Xilinx Spartan-3 documentation, but the EVAL-ADV793xFEZ schematic does not indicate what package is being used, so I have no way to tell.)

    2b. The clock, 16-bit pixel data, HSYNC, and VSYNC from the ZCU102 must be sent into the Expansion Port (J4) as 1.8V LVCMOS signals.  (3.3V LVCMOS is not an option over the FMC connector.)  So the main thing I need to know is that the EXP_CLK, D[0:15], EXP_VS, and EXP_HS signals from the Expansion Port are going into the Spartan-3 FPGA on banks 0,1,2, or 3.  Is this true?

    3. On page 6 of the EVAL-ADV739xFEZ schematic, there is a note for FPGA-VAR3V3 that implies the voltage level is variable.  But FPGA-VAR3V3 is connected to a linear regulator that is fixed at 3.3V.  Is the FPGA-VAR3V3 voltage level really variable?  If so, how do we change this to be 1.8V?

  • After doing some more reading, I think I can answer some of my own questions:

    1. Yes, I would have to connect the ZCU102 to the J4 Expansion Port on the EVAL-ADV739xFEZ front-end board.

    2a & 2b. After looking at the Xilinx Spartan-3 documentation in more detail, I was able to figure out that the package being used is the TQ144, and that I/O banks 0,1,2,3 covers the Top and Right sides of the FPGA when viewed from above.  So I/O banks 0,1,2,3 do indeed cover all the signals from the J4 Expansion Port, as well as the signals going out to the EVAL-ADV7393 back-end board over the J5 connector.

    Please let me know regarding my earlier question #3.  I'm still at a loss as to how the FPGA-VAR3V3 can be switched between 3.3V and 1.8V as it looks to be connected to a linear regulator that is fixed at 3.3V output.

  • This board was done before my time but here is an educated guess as to what is going on.

    Originally the board was designed with the concept of tying into another FPGA board which might have different input ports besides just 3.3V.  If you remove the EMI filter (F7) then the off board FPGA can supply the correct voltage to power up the associated port pins on the Spartan FPGA.  

    Since then we've only built the board with 3.3V rails in mind.  For you it might be best to keep every at 3.3V.