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ADV7611 ADV7619 image shifting.

Hi, 

I have a question regrading ADV7611/19 chips. I have a device  which does alter the input tmds clock to adv7611/19 , when is trying to genlock. Sometimes I am getting image shifting during the genlock process. I noticed that during initial steps of genlock process  DC_FIFO_LOCKED goes low and after high.  I noticed a huge improvement in my case when in the DPLL address register 0xc3 to 0x80 and 0x3F to 0x03. Initial value for this register was 0x"00". Video resolution tested :1920x1080x30Hz(pixel clock = 74.25 Mhz) and 1920x1080x60Hz(pixel clock = 148.5 Mhz). I was thinking that the issue with image shifting is caused by  video fifo underflow/overflow condition and I noticed that DPLL is disable for pixel clock greater than 170 Mhz. In the recommended register setting document I manage to find the above register settings. 

Question :

1. What are those register ? I am not able to find any description in the datasheet. 

2. Is it safe to have those register settings for all modes ? What are the implication of setting those register for those values for all modes ? 

Thank you. 

  • Hi,

      DPLL must be bypassed when video with pixel clock rate above 170 MHz and in that FIFO is clocked by 1x TMDS PLL clock.

    1. What are those register ? I am not able to find any description in the datasheet.

           Those registers are ADI required writes since "ADI Required Writes" are proprietary configuration optimization writes. These were determined during original chip bring up and evaluation. They are required writes. We will not release their definition or function to the public.

           As per the script 98 F8 4C ; DPLL
             4C C3 80 ; ADI Required Write
             4C CF 03 ; ADI Required Write

    As per expert comment regarding DPLL 0xA0 "Better to leave it in automatic mode as it is by default .

    Note:  During silicon evaluation and optimization ADI design and evaluation teams will optimize internal processing blocks through I2C adjustments. The part will subsequently be qualified and tested with this configuration. We regard these writes as non-user adjustments and hence their function is not documented.

    Thanks,

    Poornima

  • Hi Poornima, 

    You're saying that "DPLL must be bypassed when video with pixel clock rate above 170 MHz and in that FIFO is clocked by 1x TMDS PLL clock"  . How do you disable the DPLL ? 

    Regarding ADI required write I understand. I can confirm that when image shifting I can see that DC_FIFO_LOCKED goes from high to low and high again. What other things I can change on ADV7611/19 in order to stop DC_FIFO_LOCKED going low. When I am referring to "other things" I am referring  to  ADV7611/19 register that are not "ADI required"

    Kind regards,

    Cosmin

  • Hi,

    How do you disable the DPLL ? 

      By using register LLC_DLL_MUX R/W (0x33) we can control to apply the pixel clock DLL to the pixel clock output on the LLC pin

       0 - Bypasses the DLL
       1 - Muxes the DLL output on LLC output

    I believe if DCFIFO_LEVEL is varying, there might be a problem with input to lock stable. Issues at 170MHz might be due to power supply stability, poor layout and sources with excessive tmds clock jitter .

     Please let us know, Have you checked with anyother source ?

    Note:  If you see any image disruption, In that case "Suggestion from the expert was to disable the DC_FIFO and forcing the source video to be 8-bits" by completely bypass the CP - 0xBF[0] CP_COMPLETE_BYPASS_IN_HDMI_MODE = 1

    0xBF[0] CP_COMPLETE_BYPASS_IN_HDMI_MODE = 1 will completely bypass the CP and see if the problem is related to the DCFIFO.

    Thanks,

    Poornima

  • Click here to play this videoHi, 

    1. Is DPLL = DLL ? 

        I am referring to DPLL inside Video Fifo 

    2. Just to confirm CP - 0xBF[0] CP_COMPLETE_BYPASS_IN_HDMI_MODE  , that register is in HDMI map or CP map ? If I do on CP map I get a blue color being displayed.

    Please find above a video with the issue. 

    Kind regards,

    Cosmin

  • Hi,

      Please find the below comments,

    1. Is DPLL = DLL ? 

         As per expert comment,We can bypass or disable the DPLL by using register  LLC_DLL_MUX (IO Map Reg 0x33[6]):    

        Please refer here  RE: Bypass the DPLL of an ADV761x HDMI RX?

    2.Just to confirm CP - 0xBF[0] CP_COMPLETE_BYPASS_IN_HDMI_MODE  , that register is in HDMI map or CP map ?

         It is in IO MAP, Please refer Page 137 at https://www.analog.com/media/en/technical-documentation/user-guides/UG-180.pdf

    Thanks,

    Poornima

  • Hi,

    If you're bypassing the DPLL what will be the effect on the fifo inside Video Fifo block ? 

    If the effect will be only on the output clock I don't really care. In the video that I've posted earlier you could the fifo level going through different value and also you could see DC_FIFO_LOCKED going to zero.  Ideally I want to prevent DC_FIFO_LOCKED going to zero , because as you can see it affects the image badly. 

    What other things I can try in order to avoid DC_FIFO_LOCKED going to zero.?

    Thank you, 

    Cosmin

  • Hi,

    If you're bypassing the DPLL what will be the effect on the fifo inside Video Fifo block ? 

         I beleive ,bypassing the DPLL will not effect anything on the video FIFO block.

    What other things I can try in order to avoid DC_FIFO_LOCKED going to zero.?

     Please let us know, Are you using any spread spectrum source.

     If So, Please ensure with below things.

     First Can you turn off the spread-spectrum and if so does the 7619 receive correctly?

     Second, when in spread spectrum mode does the source meet the HDMI 1.4b specification clock jitter, i.e. is the eye correct?

    Third, you need the specs on exactly what the source is doing to the signal as far as modulation frequency and frequency deviation.

     NOTE:  Generally this DC FIFO registers we can use it for diagnostic purposes which will indicate the video FIFO status So depending upon that we know the status of the incoming video.
         If it is overflow or underflow, In that case we need to control the FIFO registers for normal operation then only we will get the appropriate video output.
        As per the expert comments, " The HDMI parameters readbacks in terms of video line length/horizontal pixels/hsync porch etc in the ADV7604 appears to read correctly based on the input signal applied. The DCFIFO lock appears to be locked. While the readbacks and lock signals are good indicators, however they are not enough to say that the part will be able to process the input signal accurately. for example, the DCFIFO Level has some margin due to the input signal applied."

    Thanks,

    Poornima

  • Hi ,

    Thank you for the info. 

    I am using Quantum box as a source.The spread spectrum is turned off. 

    You're saying in your previous poet " If it is overflow or underflow, In that case we need to control the FIFO registers for normal operation then only we will get the appropriate video output."   How to do it ? 

    Kind regards,

    Cosmin

  • Hi,

       Could you please try settings the FIFO registers by referring the section VIDEO FIFO on Page 37.

       We don't have any reference FIFO registers settings, Usually this video FIFO is designed to operate completely autonomously and It automatically re-synchronizes the read and write pointers if they are about to point to the same location. 

    Thanks,

    Poornima