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[ADV7480] Layout guideline

Hi team,

I'm looking for guidelines on the layout of the ADV7480.

I got the Hardware manual from ADV7480 support files and read the comments about layout.

I think that we need  more specific guideline.

Is there any other layout guideline?

I have two question for layout.


I'm going to make the MIPI and HDMI data lanes and CLK traces as long as possible, but how much difference can the ADV7480 tolerate?

The datasheets for other devices said:

"A good practice is to match the trace lengths for a given group of four channels to within 0.05 inches on FR4 material."

Can the ADV7480 be considered the same?


Our circuit adds CMCs to the data lines and clock line.

Are there any restrictions when arranging multiple CMCs?

Place it as close to the connector as possible, but is it okay to rotate only some CMCs by 45 ° or 90 ° due to space constraints?

Since the CMCs are close to each other, I am worried that they may interfere with each other.

Best regards,


  • Here's a HDMI layout guide

     HDMI Layout Guideline 

    I am not sure what CMC refers to.  if is ESD protection then place them close to the connector.

  • Hi GuenterL-san,

    Thank you for your support.

    >I am not sure what CMC refers to.  if is ESD protection then place them close to the connector.

    I'm sorry. I used CMC to mean a common mode choke coil.

    Common mode choke coils and ESD protection elements can be placed near the connector, but the Common mode choke coils cannot be aligned in the same orientation..

    I am thinking of rotating the common mode choke coil to 45 degrees and 90 degrees and arranging four.

    I would like to know if that is no problem. 

    I'm reading the HDMI layout guidelines you taught me.

    I have a question about a trace length mismatch.

    The layout guidelines assume that CLK is 297MHz.

    For example, if CLK is set to 100MHz, that is, 1/3 of 297MHz, can the index related to trace mismatch in the layout guideline be considered as 3 times?

    Is it okay to think of ± 3mm as ± 9mm?

    In addition, the calculated value of Intra-pair SKEW was 7.57 mm, but the requirement is stricter as ± 3 mm.

    For what reason is this so severe?

    Is it equivalent to ± 3mm assigned to the PCB in consideration of the connector and cable?

    Best regards,


  • Hi T-yoshi,

    CMC = Common Mode Choke, good to know

    Placement of the CMC not as important as placing the ESD protection.  With ESD protection you want to place it as close to the entry point as possible, i.e. the connector.  CMCs can be placed anywhere in the signal path.

    The calculations were done assuming 3840x2160p30 with 8 bit color color depth.  The data rate would be 297MHz * 10 * (8 / 8) = 2.97GHz.  For 1080p60 with 8 bit color depth the data rate would be 148MHz * 10 * (8 / 8) = 1.48GHz.  If your pixel rate is less then 1080p60 and only 8 bit color depth you can loosen up the tolerance.  The same basic math still applies.

    Assuming 100Mhz pixel rate and 8 bit color depth the data rate would be 100MHz * 10 * ( 8 / 8) = 1GHZ, or 1/3 the worst case format.  Note that HDMI uses 8b10b encoding.

    Regarding 7,57mm intra-pair skew, if you assume one trace is +3mm and the other is -3mm then you would have 6mm difference between the two traces.  The math says 7.57mm and I just choose 6mm represented by the +-3mm number.

    All calculations assume the cable and connectors are prefect.  In general skew in the cable and connectors would be very small due to their construction methods. 

    The bottom line is you can loosen up the tolerance if you are not running at the worst case format however meeting these spec's should not be difficult.

  • Hi GuenterL-san,

    Thank you for your support.

    Fortunately, our system has a slow data rate, which makes it a little over ± 3mm, but we found that intra-pair skew has a margin.

    In the next prototype, we will try to make the trace lengths as same as possible.

    Best regards,