These is a video processing project I run like this : PC------(hdmi)-------> ADV7611-------(RGB24 SDR)--------> FPGA. The captured video stream is processed in FPGA.
In FPGA, some processings must be processed in the clock domain of ADV7611's LLC. How to imporve the quality of LLC so that can better support timing issues in FPGA.
I just made a prototype to demonstrate the processings. I found these is slight blink in few pixels when process to the static bmp pictures.
The quality LLC signal is potentially one of the root cause of this blink.