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PAL encoders: ADV7341, ADV7391 Driver support for ARM


We have used ADV7341 and  ADV7391 for PAL encoding with the ARM processor. But we are not getting driver support. Since we want to push the system for large scale production and PAL output is important, kindly provide the driver asap.



  • Hi,

      Here you can find the driver for ADV734x & ADV739x Encoder which is based on Linux[]=adv7393

      But i beleive you can make use this driver based on your processor support.



  • Dear Poornima,

    We have tried a lot and reached the stage: Below is the register setting applied for 720x576 output:

    i2cset -y -a 4 0x2b 0x17 0x02
    sleep 2
    i2cset -y -a 4 0x2b 0x00 0xFC
    i2cset -y -a 4 0x2b 0x01 0x80
    i2cset -y -a 4 0x2b 0x02 0x10
    i2cset -y -a 4 0x2b 0x80 0x11
    sleep 2
    i2cset -y -a 4 0x2b 0x82 0xCA
    i2cset -y -a 4 0x2b 0x84 0x00
    i2cset -y -a 4 0x2b 0x86 0x02
    i2cset -y -a 4 0x2b 0x87 0xA0
    i2cset -y -a 4 0x2b 0x88 0x10
    i2cset -y -a 4 0x2b 0x8A 0x09 [ NOTE: If we write 0x0C then image is not coming on display ]
    i2cset -y -a 4 0x2b 0x8C 0xCB
    i2cset -y -a 4 0x2b 0x8D 0x8A
    i2cset -y -a 4 0x2b 0x8E 0x09
    i2cset -y -a 4 0x2b 0x8F 0x2A
    i2cset -y -a 4 0x2b 0x84 0x08
    i2cset -y -a 4 0x2b 0x86 0x03

    On processor side below is the panel configuration on display driver located at

    static const struct drm_display_mode pdic_display_adv_mode = {
    .clock = 27000,
    .hdisplay = 720,
    .hsync_start = 720 + 12, //h_active_area + FP
    .hsync_end = 720 + 12 + 63, //h_active_area + FP + PW
    .htotal = 720 + 12 + 63 + 69, //h_active_area + FP + PW + BP
    .vdisplay = 576,
    .vsync_start = 576 + 4, //v_active_area + FP
    .vsync_end = 576 + 4 + 3, //v_active_area + FP + PW
    .vtotal = 576 + 4 + 3 + 42, //v_active_area + FP + PW + BP
    .vrefresh = 25,

    REALLY need your help in panel timing for 720x576 resolution on PAL output and register setting for
    ADV7341 chip

  • The above settings output image is as follows

  • Hi,

      Please let us know, whether you are generating the test pattern for PAL.

       If is an PAL test pattern, Please make sure with below register settings and let us know the result.

         0x17  - 0x02
         0x00 - 0xFC
         0x82 - 0xC9
         0x84 - 0x40
         0x80 - 0x11
         0x8C - 0xCB
         0x8D - 0x8A
         0x8E - 0x09
         0x8F - 0x2A



  • Thanks for the input.

    We can see test-pattern after applying provided register settings. Here, we have one doubt regarding 0x8A register.
    As per our understanding and design, It should be 0x0C[Timing Mode 2 (slave). HSYNC/VSYNC synchronization] as SOC is going to provide HSYNC and VSYNC to ADV7341. But here, ADV7341 is not showing anything on display after writing 0x0C in 0x8A register.
    We are trying to configure ADV7341 for 720x756 resolution and for that applied all Horizontal and vertical related setting as per previous comments. Do you think there is problem with horizontal and vertical parameter?
    Please provide ADV7341 register settings and Horizontal HF,HB,HSYNC,VF,VB,VSYNC for 720x576[P/I] resolution.

  • Hi,

       Please check the sync timing control on Page69 - EXTERNAL HORIZONTAL AND VERTICAL SYNCHRONIZATION CONTROL.
      Also try to configure the 0x8B register when it is in Master Mode.

    Note: Master mode is only valid when the input is BT.656.  The chip will output V & H syncs when in BT.656 and Master mode.  If doing BT.656 and in slave mode , V & H sync are inputs but ignored.



  • Hi,

    Request to review below settings applied on ADV and Processor side, resolution configured was 1440x288.

    ADV settings applied as mentioned in below table,

    Register Address

    Values set































    HSYNC and VSYNC timing settings on processor side,

    static const struct drm_display_mode pdic_display_adv_mode = {

    .clock = 27000,

    .hdisplay = 1440,

    .hsync_start = 1440 + 24, //h_active_area + FP

    .hsync_end = 1440 + 24 + 126, //h_active_area + FP + PW

    .htotal = 1440 + 24 + 126 + 138, //h_active_area + FP + PW + BP

    .vdisplay = 288,

    .vsync_start = 288 + 2, //v_active_area + FP

    .vsync_end = 288 + 2 + 3, //v_active_area + FP + PW

    .vtotal = 288 + 2 + 3 + 19, //v_active_area + FP + PW + BP

    .vrefresh = 50,


    With above settings on ADV and Processor we are able to see video out as shown in below image, picture is vertically stretched and some portion of picture is cut vertically on left edge.

    video output on monitor connected to ADV pal out

    For these settings waveforms are captured on processor’s HSYNC and VSYNC and composite video signal output from ADV.

    C1: Hsync from processor (input to ADV S_HSYNCN)

    C2: Vsync from processor (input to ADV S_VSYNCN)

    C3: Video out from ADV (Output of DAC1)

    Vsync freq 50Hz –

    Vsync signal – attached waveform_vsync_2.jpeg

    Hsync freq 15.6KHz – attached waveform_hsync_1.jpeg

    Hsync signal – attached waveform_hsync_2.jpeg

    Queries for these settings

    1. Is 1440x288 resolution valid? If it is valid then, what could be the cause of vertically stretchered picture on video output.

    2. To set the 720x576 non-interlaced video output what changes are required in settings explained above.

  • Hi,

       Please find the below comments,

    1. Is 1440x288 resolution valid? If it is valid then, what could be the cause of vertically stretchered picture on video output.

          As per specification, ADV734x can support 288p/50 Hz input but it should be configured for PAL operation and and Subaddress 0x88, Bit 1 should be set to 1.

          Also Make sure whether you are giving 16 bit RGB input, Since you have configured 16 bit RGB in 0x88 register.


          Also Please note, try to disable the PLL and check whether the noise disappears.
          If the the issue disappears with the PLL disabled is a good indicator that the problem lies in the external loop filter circuitry. The external loop filter circuit is extremely sensitive, and connecting it to an unfiltered supply will most likely in all cases lead to poor performance.

    Any noise on the external loop filter circuit supply can cause an poor performance.

    Please ensure with reference schematic and Is the external loop filter circuit connected directly to the PVDD supply without supply filtered (i.e EXT_LF filter parts directly to 1.8V without filter caps).

    2. To set the 720x576 non-interlaced video output what changes are required in settings explained above.

        Since 720/576 will come under ED/HD standard So Please use Table 85 for ED Configuration Scripts .



  • Hi,

    1. For 1440x288 resolution we have set register 0x88's bit 1 to 1(high).

    And RGB input we have configured the 0x88's register -SD input format to [1,0] as the datasheet we are referring to has mentioned to set it [1,0] for 10-bit YCbCr input/16-/24-/30-bit RGB. please see below snap of data sheet -

    We also tried disabling PLL, by disabling it improvement on the display is observed and we are looking in to it for further improvements and checking schematic for external loop filter.

    Also, I would like to add one more observation we have, on display connected to ADV output, white color background becomes light blue. Can you please guide us to resolve this light blue color issue?

    2. We tried setting up the test pattern for ED mode, by setting registers of ADV as below, but not able to see any thing on connected display.

    i2cset -y -a 4 0x2b 0x17 0x02
    i2cset -y -a 4 0x2b 0x00 0x1C
    i2cset -y -a 4 0x2b 0x01 0x70
    i2cset -y -a 4 0x2b 0x02 0x24
    i2cset -y -a 4 0x2b 0x30 0x18
    i2cset -y -a 4 0x2b 0x31 0x0D
    i2cset -y -a 4 0x2b 0x0B 0x40
    i2cset -y -a 4 0x2b 0x36 0xEB
    i2cset -y -a 4 0x2b 0x37 0x80
    i2cset -y -a 4 0x2b 0x38 0x80

    Can you please share the details to enable test pattern of ED mode?