How do we limit the MCLK Output frequency on the HDMI Receivers?

Hi,

 MCLK is derived from the TMDS clock and the information in the audio infoframe.

 This audio master clock is used to clock the audio procession section So depending upon the processor(DSP) requirement we can set the MCLK with certain range (128fs/256fs/512fs)

 And this 'MCLK_FS_N[2:0]' register would select the frequency of MCLK out as multiple of 128fs.

Thanks,

Poornima

Is it necessary to write 0xD4[3:0] and 0xD5 and 0xCF[0] per MCLK(MCLK_FS_N[2:0] setting)?

Hi Masatoshi San,

  Its not required (If your requirement meets the MCLK that is set by using "MCLK_FS_N[2:0] "register) .

  If in case if your project want to limit the Maximum and Minimum MCLK output frequencies and then use '0xD4/0xD5' registers accordingly to acheive this.

Thanks,

Poornima