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[ADV7480] Output status during MIPI-CSI Tx Power-up/Power-down sequence


In the MIPI CSI TxA power-up / power-down sequence,

could you tell me the state of MIPI output after each register is set?

1) Execute the following CSI TxA power-down sequence during video output.


2) From the above power-down sequence, execute the following power-up sequence.


MIPI status : LP-11, LP-01, LP-00, HS in the figure below

MIPI clock status : Output / Stop (In case of stop, please describe if there is a stop with "L" or a stop with "H".)


Best regard. 

  • Hi,

      Here we don't have MIPI reference termination board to do the MIPI-CSI Tx power up & power down signalling measurements with suggested registers.

      Please refer below expert comment about 'CSITX_PWRDN' sequence,

        CSITX_PWRDN bit will power up or down the Tx and this roughly equates to enabling or disabling the clock lane.

        But it is not as simple as the CSITX_PWRDN bit toggling a LP-HS transition directly.

    In the case of LP state initially, when the CSITX_PWRD bit is used to enable the Tx its does not start transmitting straight away as the clock line is held static and only released later with i2c writes. This is to ensure there is a compliant LP - HS transition.

    Likewise when CSITX_PWRD bit is used to disable the Tx, the outputs will not immediately go into LP state from HS. The transmitter will finish out the current video line.

    So yes you can more or less force LP or LP-HS transition by just toggling the CSITX_PWRDN bit but for a fully MIPI standard compliant LP-HS transition you would need to sequence the CSITX_PWRDN with the control of the clock lane output as the scripts do.

    Note:  MIPI CSI-2 transmitter conforms to the MIPI D-PHY Version 1.00.00 specification and it therefore conforms to the AC timing specifications in the MIPI D-PHY Version 1.00.00 specification.

    To guarantee optimal operation, the MIPI CSI-2 receiver should also conform to the MIPI D-PHY Version 1.00.00 specification.