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Horizontal stripes appear in the output of ADV7186

Hi,

The customer's system uses the ADV7186 as a video decoder to capture NTSC video.

The video input to the ADV7186 is analog NTSC.

This system is already on the market, and recently a phenomenon of horizontal stripes

appearing on the right side of the screen has occurred.

The figure below shows the phenomenon during cold boot.

What is the cause of this phenomenon?

What kind of anomaly can be estimated on the input line?

I would be grateful if you could answer as soon as possible.

Best regards. 

Parents
  • Hi,

     ADV718x does not use frame memory, so an image cannot be stored. If there are issues with the output timing/ alignment, there is an possibility for getting an image with above reported horizontal stripes.
       Possible causes
        - Incorrect capture in the downstream device - Incorrect timing/ Start of active video.
        - Incorrect analog image from source e.g. Camera itself.  
        Normally in NTSC mode the ADV718x outputs a 60 Hz field rate.
         Does your screen match this 60Hz or is it 50 Hz ? This may could also can cause jitter.                                      

    Also please note by default the ADV718x video decoders receive analog video and output digital video in accordance with the "ITU-R BT.656-3" standard.
    If the receiver system is expecting an ITU-R BT.656-4 output from the ADV718x then this can result in 10 lines of black video being output at the top of the screen.

    Setting User Map, Address 0x04[7] to 1 will program the ADV718X to output video in accordance with the ITU-R BT.656-4 standard.
    This generally occurs with NTSC CVBS video inputs but not with PAL CVBS inputs. This is because of difference in the blanking timing between the ITU-R BT.656-3 and ITU-R BT.656-4 standards for digitised NTSC.


    Thanks,

    Poornima

  • Hi,

    Thank you for your reply.

    There was an additional confirmation request from the customer.

    In the above, it is described as "- Incorrect timing / Start of active video."

    What part of the datasheet is this pointing to?

    Best regard.

  • Hi,

    In the above, it is described as "- Incorrect timing / Start of active video."

         Above possible causes we have taken from the expert  suggestion

    Below are the expert suggested possible causes,

         ADV7180 does not use frame memory, so an image cannot be stored. If there are issues with the output timing/ alignment,

    Possible causes

    - incorrect capture in the downstream device - incorrect timing/start of active video.

    - Incorrect analog image from source e.g. Camera itself.  

    Thanks,

    Poornima

Reply
  • Hi,

    In the above, it is described as "- Incorrect timing / Start of active video."

         Above possible causes we have taken from the expert  suggestion

    Below are the expert suggested possible causes,

         ADV7180 does not use frame memory, so an image cannot be stored. If there are issues with the output timing/ alignment,

    Possible causes

    - incorrect capture in the downstream device - incorrect timing/start of active video.

    - Incorrect analog image from source e.g. Camera itself.  

    Thanks,

    Poornima

Children
  • Hi,

    Thank you for your reply.

    I would like to confirm a little more.

    Is the content described in "Possible causes" related to the sequence of video signals?

    Could you tell me if the related signal is only the INPUT line of the video signal?

    Best regard.

  • Hi,

      The Possible cause which i was mentioned like from the Source & Sink device.

       Please note crosscheck with reference schematic, If you followed the basic circuits and layouts used in the reference designs then you should not have a problem in this case. All power rails can affect the output images,it just the PVDD is most sensitive to noise. PVDD is very important maintaining video stability.

      As per expert comment, PVDD is very important maintaining video stability.

      Ideally it should be ferrite bead isolated from other supplies and the data sheet reference schematic does not show this which is OK if the PVDD source is very clean. 

      First check PVDD noise both high frequency and lower frequencies around the horizontal rates.  If noise is coupled into PVDD then the PLL might lose lock and causing image issues.

    Thanks,

    Poornima