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ADV7842 Register programming

For ADV7842 Register programming, data writing as per following script.

Here As per my understanding I2C IO Map address is 0x40, and next addresses are programmable but before accessing 0x40 I2C, 0x50 is accessing, what is the existence of 0x50 I2C slave address. 

:1-1a CVBS NTSC_PAL-M  480i H_V_DE 10bit out HDMI:
50 10 05 ; 36 output through AVO1,AV02,DACs
50 11 08 ; Bus Reversal
50 19 10 ; ADV7842 Mode
50 1B 02 ; ADV7511
40 FF 80 ; I2C reset
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
40 F1 90 ; SDP map
40 F2 94 ; SDPIO map
40 F3 84 ; AVLINK
40 F4 80 ; CEC
40 F5 7C ; INFOFRAME
40 F8 4C ; AFE
40 F9 64 ; KSV
40 FA 6C ; EDID
40 FB 68 ; HDMI
40 FD 44 ; CP
40 FE 48 ; VDP
50 20 00 ; De-assert HDP
40 00 01 ; CVBS 4x1 mode
40 01 00 ; SD core
50 20 00 ; De-assert HDP
40 03 01 ; 10 bit Mode
40 04 82 ; Output bus rotation
40 0C 40 ; Power up Core
40 15 80 ; Power up pads
40 19 83 ; LLC DLL phase
40 33 40 ; LLC DLL enable
4C 00 0E ; ADC0 power Up
4C 02 80 ; Manual Mux
4C 03 B0 ; Ain11
4C 0C 1F ; ADI recommended write
4C 12 63 ; ADI recommended write  
94 7A A5 ; Timing Adjustment
94 7B 8F ; Timing Adjustment
94 60 01 ; SDRAM reset
94 97 00 ; Hsync width Adjustment
94 B2 60 ; Disable AV codes
90 00 7F ; Autodetect PAL NTSC SECAM
90 01 00 ; Pedestal Off
90 03 E4 ; Manual VCR Gain Luma 0x40B
90 04 0B ; Manual Luma setting
90 05 C3 ; Manual Chroma setting 0x3FE
90 06 FE ; Manual Chroma setting
90 12 05 ; Frame TBC,3D comb enabled
90 A7 00 ; ADI Recommended Write
72 01 00 ; Set N Value(6144)
72 02 18 ; Set N Value(6144)
72 03 00 ; Set N Value(6144)
72 15 03 ; 12 bit 422 YCbCr input
72 16 E7 ; Input Style
72 18 46 ; CSC disabled
72 40 80 ; General Control packet enable
72 41 10 ; Power down control
72 48 08 ; Data right justified
72 49 A8 ; Set Dither_mode - 12-to-10 bit
72 4C 00 ; 8 bit Output
72 55 20 ; Set YCrCb 422 in AVinfo Frame
72 56 08 ; Set active format Aspect
72 96 20 ; HPD Interrupt clear
72 98 03 ; ADI Recommended Write
72 99 02 ; ADI Recommended Write
72 9C 30 ; PLL Filter R1 Value
72 9D 61 ; Set clock divide
72 A2 A4 ; ADI Recommended Write
72 A3 A4 ; ADI Recommended Write
72 A5 44 ; ADI Recommended Write
72 AB 40 ; ADI Recommended Write
72 AF 16 ; Set HDMI Mode
72 BA 60 ; No clock delay
72 D1 FF ; ADI Recommended Write
72 DE 9C ; ADI Recommended Write
72 E4 60 ; VCO_Swing_Reference_Voltage
72 FA 7D ; Nbr of times to search for good phase
End

Thanks & Regrads,

Mallikarjuna B.

Parents
  • Hi,

     These scripts were originally written for the ATV motherboard.  Device address 0x50 corresponds to an FPGA on that board and can be ignored when configuring the EVAL-ADV7842-7511 and EVAL-ADV7612-7511 evaluation boards. 

    Note: 44 is ADV7842 CP

               4C is ADV7842 AFE

               50 is the FPGA on the ATV Motherboard

               68 is ADV7842 HDMI

               90 is ADV7842 SDP

               94 is ADV7842 SDPIO

    Please note that most of these addresses are software programmable. The scripts sets the address (in the main/IO map) before writing to them.

    Thanks,

    Poornima

Reply
  • Hi,

     These scripts were originally written for the ATV motherboard.  Device address 0x50 corresponds to an FPGA on that board and can be ignored when configuring the EVAL-ADV7842-7511 and EVAL-ADV7612-7511 evaluation boards. 

    Note: 44 is ADV7842 CP

               4C is ADV7842 AFE

               50 is the FPGA on the ATV Motherboard

               68 is ADV7842 HDMI

               90 is ADV7842 SDP

               94 is ADV7842 SDPIO

    Please note that most of these addresses are software programmable. The scripts sets the address (in the main/IO map) before writing to them.

    Thanks,

    Poornima

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