ADV7482 update speed for the peak white algorithm by LAGT

Hi,

  The peak white algorithm is designed to detect if the input signal is close to the limit and dramatically reduce the gain in the ADV7482 to prevent the signal becoming clipped.

  Please refer attached AGC and peak white operation pdf at ADV7180_Peak_White.pdf

  The update speed for the peak white algorithm can be customized by the use of internal parameters. Please refer Page 58 in ADV748x Hardware Manual at 7026.ADV748x_Manuals.zip

   Here also you can find the details about LAGT at 0407.ADV7181C_Manuals.zip 

Thanks,

Poornima

Hi,

Thank you for your reply.

I understand we can select the update speed for the peak white algorithm can be customized by lagt[1:0] register.
However, the lagt chart does not have a default reference time.

Please let me know the update spped at default(lagt[1:0]=11, adaptive).

Regards,

Gattu

Hi,

 When LAGT is '11(default)' then the speed will be  dependent on VID_QUAL.

 Also please note this LAGT[1:0] will only be effective when LAGC[1:0] is set to auto gain
(001,010,011or 100).

Thanks,

Poornima

Hi,

"When LAGT is '11(default)' then the speed will be dependent on VID_QUAL."

I checked the hardware manual, but the details of "VID_QUAL" were not described in it. Please let me know more details about "VID_QUAL".

Regards,
Gattu

Hi,

Yes its not provided in the ADV7181D manuals.

"VID_QUAL" allows the user to influence the time constant of the system depending on the input video quality. 

Thanks,

Poornima

Hi,

"VID_QUAL" allows the user to influence the time constant of the system depending on the input video quality."

Do you have " time constant" or how should I calculate the value?

Regards,

Gattu

Hi,

 In simple we can say "VID_QUAL" is depending on the input video coming from the source.

In ADV7181D we dont have any register configuration but previous chipset like ADV7183 they have provided the register configuration for VID_QUAL at  https://www.analog.com/media/en/technical-documentation/obsolete-data-sheets/ADV7183.pdf - Page32

Thanks,

Poornima

Hi,

 In simple we can say "VID_QUAL" is depending on the input video coming from the source.

In ADV7181D we dont have any register configuration but previous chipset like ADV7183 they have provided the register configuration for VID_QUAL at  https://www.analog.com/media/en/technical-documentation/obsolete-data-sheets/ADV7183.pdf - Page32

Thanks,

Poornima

Hi,

Thank you for the detailed explanation on the feature, I'm going to check it.

Regards,

Gattu