ADV7181C CP configuration for PAL square pixel RGB

Hi all,

We have a board with ADV7181C decoder and we need to config it in the following mode:

  1. The input signal is RGB with sync on green, PAL format, 768x576 visible pixels.
  2. The output data should be 16 bit 4:2:2 YCbCr.

 

Is the ADV7181C compatible with PAL square pixel using the Component Processor (CP)?

I tried the bit [2] of reg 0x01 but it doesn’t appear to do anything. Is there a hidden register with the same function for CP?

How can I configure the decoder? Is it possible in non-standard input?

I haven’t been able to have the free run mode working either with this video format.

I tried to follow a few examples I found on this forum, but I doesn’t work for me. 

Thanks, Romain

Parents
  • Hi 

    I managed to get it to work with a custom configuration. I was already looking into the registers that  mentioned, it reassured me that I was on the right track.

    The first part of the configuration resemble to the many example anybody can find of this forum:

    The first part of the configuration resembles to the many example anybody can find of this forum:
    0x05 0x01; Prim_Mode = 0001b for CP-Mode
    0x06 0x01; VID_STD = 0001b for CP 2x2 625i
    0x1D 0x47; Enable 28MHz Crystal
    0x3A 0x10; Set Latch Clock 01b LLC range 13.5MHz - 55MHz
    0x3C 0x5B; PLL_QPUMP to 011b (250uA)
    0x6B 0xC3; Select 422 16 bit YPrPb out from CP
    0x86 0x0B; Enable "new" stdi_line_count_mode
    0xC3 0x56; Manual Muxing - ADC0=AIN6(G), ADC1=AIN6(G)
    0xC4 0x84; Manual Muxing - ADC2=AIN4(B), enabled manual muxing
    0xF3 0x00; Manual Muxing - ADC3= unconnected, anti_aliasing enabled for ADC 0,1,2,3

    # This next part is to set the correct number of pixels per line
    0x87 0xE3; TPLL Pix_freq / F_hsync ==> 14.75MHz / 15625 Hz = 944 >> 0x3B0
    0x88 0xB0; TPLL Pix_freq / F_hsync ==> 14.75MHz / 15625 Hz = 944 >> 0x3B0
    0x8A 0x90; Enable Manual VCO_RANGE=00
    0x8F 0x07; FR_LL to 1833 & Enable 28.63MHz LLC (28636363 / 15625 = 1832.7272) (0x729)
    0x90 0x29; FR_LL to 1833 & Enable 28.63MHz LLC (28636363 / 15625 = 1832.7272) (0x729)

    # This part is to set the position of hsync and its duration
    # I am using AVcode so I tweaked the duration of hsync to get 768 active pixels per line
    0x7B 0x1A; SAV at falling edge of Hsync, EAV at rising edge of Hsync (depends on polarity of hsync)
    0x7C 0x0C; START_HS early, END_HS later
    0x7D 0x16; END_HS later
    0x7E 0xEA; START_HS early

    # It seems that the first line was ignored, and 1 line of blanking was considered active
    # so, I positioned vsync 1 line earlier
    0x7F 0xFF; START_VS early, END_VS early

    It is needed to set the CSC coefficients to convert the RPG input signal to YCbCr422

    0x52 0x00; CSC
    0x53 0x00; CSC
    0x54 0x12; CSC
    0x55 0x90; CSC
    0x56 0x38; CSC
    0x57 0x69; CSC
    0x58 0x48; CSC
    0x59 0x08; CSC
    0x5A 0x00; CSC
    0x5B 0x75; CSC
    0x5C 0x21; CSC
    0x5D 0x00; CSC
    0x5E 0x1A; CSC
    0x5F 0xB8; CSC
    0x60 0x08; CSC
    0x61 0x00; CSC
    0x62 0x20; CSC
    0x63 0x03; CSC
    0x64 0xD7; CSC
    0x65 0x19; CSC
    0x66 0x48; CSC
    0x67 0x13; CSC

    I hope this will help someone else

Reply
  • Hi 

    I managed to get it to work with a custom configuration. I was already looking into the registers that  mentioned, it reassured me that I was on the right track.

    The first part of the configuration resemble to the many example anybody can find of this forum:

    The first part of the configuration resembles to the many example anybody can find of this forum:
    0x05 0x01; Prim_Mode = 0001b for CP-Mode
    0x06 0x01; VID_STD = 0001b for CP 2x2 625i
    0x1D 0x47; Enable 28MHz Crystal
    0x3A 0x10; Set Latch Clock 01b LLC range 13.5MHz - 55MHz
    0x3C 0x5B; PLL_QPUMP to 011b (250uA)
    0x6B 0xC3; Select 422 16 bit YPrPb out from CP
    0x86 0x0B; Enable "new" stdi_line_count_mode
    0xC3 0x56; Manual Muxing - ADC0=AIN6(G), ADC1=AIN6(G)
    0xC4 0x84; Manual Muxing - ADC2=AIN4(B), enabled manual muxing
    0xF3 0x00; Manual Muxing - ADC3= unconnected, anti_aliasing enabled for ADC 0,1,2,3

    # This next part is to set the correct number of pixels per line
    0x87 0xE3; TPLL Pix_freq / F_hsync ==> 14.75MHz / 15625 Hz = 944 >> 0x3B0
    0x88 0xB0; TPLL Pix_freq / F_hsync ==> 14.75MHz / 15625 Hz = 944 >> 0x3B0
    0x8A 0x90; Enable Manual VCO_RANGE=00
    0x8F 0x07; FR_LL to 1833 & Enable 28.63MHz LLC (28636363 / 15625 = 1832.7272) (0x729)
    0x90 0x29; FR_LL to 1833 & Enable 28.63MHz LLC (28636363 / 15625 = 1832.7272) (0x729)

    # This part is to set the position of hsync and its duration
    # I am using AVcode so I tweaked the duration of hsync to get 768 active pixels per line
    0x7B 0x1A; SAV at falling edge of Hsync, EAV at rising edge of Hsync (depends on polarity of hsync)
    0x7C 0x0C; START_HS early, END_HS later
    0x7D 0x16; END_HS later
    0x7E 0xEA; START_HS early

    # It seems that the first line was ignored, and 1 line of blanking was considered active
    # so, I positioned vsync 1 line earlier
    0x7F 0xFF; START_VS early, END_VS early

    It is needed to set the CSC coefficients to convert the RPG input signal to YCbCr422

    0x52 0x00; CSC
    0x53 0x00; CSC
    0x54 0x12; CSC
    0x55 0x90; CSC
    0x56 0x38; CSC
    0x57 0x69; CSC
    0x58 0x48; CSC
    0x59 0x08; CSC
    0x5A 0x00; CSC
    0x5B 0x75; CSC
    0x5C 0x21; CSC
    0x5D 0x00; CSC
    0x5E 0x1A; CSC
    0x5F 0xB8; CSC
    0x60 0x08; CSC
    0x61 0x00; CSC
    0x62 0x20; CSC
    0x63 0x03; CSC
    0x64 0xD7; CSC
    0x65 0x19; CSC
    0x66 0x48; CSC
    0x67 0x13; CSC

    I hope this will help someone else

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