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ADV7280-M

My question is as follows for the ADV7280M related to MIPI CSI2. I have qty 6 ADV7280M in my design which gives me 6 MIPI clocks and Data lines. I do not have enough unused PLLs on the FPGA to pick up all the ADV7280M MIPI clocks. If I synchronize all the ADV7280M system clocks, will the MIPI clocks be in phase with one another? Therefore will I only need to pick up one ADV7280M MIPI clock on the FPGA?

  • Hi,

    Your question has been forwarded to the part specialist

    Best Regards,

    Jeyasudha.M

  • Hello,

    The ADV7280-M's will all lock to the analog video input at different times. Therefore even if the same 28.63636MHz clock is applied to the ADV7280-Ms,  the MIPI clock and data information will not be in-phase.

    Synchronizing analog video is very difficult. You could do something like having large memory buffers in your SOC that store each of video outputs from the ADV7280-Ms. You would also need the video cameras to output a frame number as ancillary data. This would allow the SOC to stitch together the relevant frames together. However this would also add to the latency through the system.

    Also you will have another problem. MIPI is designed as a chip-to-chip interface.

    The input/output termination of the Tx/Rx are constantly changing in a MIPI CSI-2 stream as the high speed and low power states are being entered/exited. Connecting more than one MIPI CSI-2 Tx together will cause the termination scheme to violate the MIPI D-PHY specification. See here for more information Are Multiple Video Streams over Single MIPI CSI-2 Link Possible on the ADV728x ?  Therefore it is not possible to simply tie the output from ADV7280-M's together.

    regards,

    Robert Hinchy

    Applications Engineer,

    Analog Devices Inc.

  • FormerMember,

    I am not planing to tie the MIPI CSI-2 outputs together. I want to use 1 mipi clock for all my D-PHY RX cores on my SOC. 

    For the ADV7280M, the MIPI Clock stays in HS once it is programmed, which is independent of the analog video locking. It seemed to me that the HS mipi clock is generated based on ADV7280M internal PLL. 

  • Ok I understand.

    You want to use a single MIPI output clock from an ADV7280-M and use that to clock the data from 6 ADV7280-M devices.

    Sorry I don't this this scheme will work. The setup and hold time specifications for the MIPI data from 5 of the ADV7280-Ms will most likely be violated.

    I will pass this information onto our marketing team to see if we could add this feature into future designs.

    Regards,

    Robert Hinchy

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