ADV7403 register configuration for STANAG 3350 CLASS B/C Video Signals

Hello, 

I am also having same setup and I have configured registers as below attached spreadsheet. I am getting the below output

For 2 different adv7403 chipset ( with same register configuration).

In the below image we can see
- yellow line in the beginning.
- Light pink instead of white.
- dotted line at the bottom of red and blue bar.

How to solve this issue? Can anyone please help?

Thanks and Regards,
Gladson

XLSX

Hi,

Please ensure with FPGA whether you are getting the proper color output from FPGA part. Generally FPGA clock outputs are not very stable or accurate.  This may cause dotted lines.
Also have you checked the power supplies, especially focus on the PVDD supply. Noise on the supplies can lead to jitter on the output.

 To avoid pink issue, Please try with below things,
      It might be the chance of getting the pink color video output when the clamp setting  are CLAMP_MAN = 0, CLAMP_A=0, So please try with below CLAMP configuration and let us know the result.
CP: CLMP_A_MAN = 1     (6C=0X80)
OR
CP: CLMP_MAN = 0, CLMP_A = 2047

     Also if the output seems pink issue which might be related to CSC, So try to adjust manually and refer with reference script. And also try to adjust color control register.  

Thanks,

Poornima

Hello Poornima,

We have attached different observation while using different scripts.
File structure is:
->script1 : script1.png - Black and white test pattern.
                 script1.txt - script
->script2 : script2.png - Half frame grep and Half black.
                 script2.txt - script
->script3 : script3.png - Yellow overlay on first half colour bars.
                 script3.txt - script
->script4 : script4.png - Swap of red and dark blue, light blue and yellow.
                 script4.txt - script
->script5 : stanag1.png - With yellow line in the beginning of white bar.
                 stanag2.png - image is more yellowish.
                 stanag3.png - image is more yellowish.
                 script5.txt - script
->testpattern.png : Expected output.

Currently we were trying to solve yellow line issue in script 5 and we are sorry to say that we could not solve it.

The register configuration mentioned in script5(refer script.zip) will affect intterupts for hotplug. We are not getting interrupt after we configure the below register.
adv7403_write(state, 0x05, 0x00);//Primary mode: Standard definition
adv7403_write(state, 0x06, 0x0A);//Video Standard : for NTSC
                                              or
adv7403_write(state, 0x06, 0x0B);//Video Standard : for PAL

Initially how we have configured interrupt registers:
Enter into User Sub Map 1 mode and configure registers and exit from User Sub Map 1.

adv7403_write(state, 0x0E, 0x20); // Enter User Sub Map
adv7403_write(state, 0x40, 0xC2); // Interrupt active until cleared, Drive High when Active
adv7403_write(state, 0x44, 0x03); // Unmask SD_LOCK_Q and SD_UNLOCK_Q
adv7403_write(state, 0x43, 0x83); // Clear SD_LOCK_Q and SD_UNLOCK_Q
adv7403_write(state, 0x4C, 0x81); // Unmask SD_OP_CHNG_Q
adv7403_write(state, 0x4B, 0xC1); // Clear SD_OP_CHNG_Q
adv7403_write(state, 0x0E, 0x00); // Exit User Sub Map

Even we tried unmasking cp lock and unlock interrupt, still we are not getting same issue
adv7403_write(state, 0x0E, 0x20); // Enter User Sub Map
adv7403_write(state, 0x40, 0xC2); // Interrupt active until cleared, Drive High when Active
adv7403_write(state, 0x44, 0x0F); // Unmask SD_LOCK_Q, SD_UNLOCK_Q and CP_LOCK_Q, CP_UNLOCK_Q
adv7403_write(state, 0x43, 0x8F); // Clear SD_LOCK_Q and SD_UNLOCK_Q
adv7403_write(state, 0x4C, 0x81); // Unmask SD_OP_CHNG_Q
adv7403_write(state, 0x4B, 0xC1); // Clear SD_OP_CHNG_Q
adv7403_write(state, 0x0E, 0x00); // Exit User Sub Map

I kindly request you to review all the scripts and guide us for the proper configuration along with interrupt configuration

Thanks and Regards,
Gladson
scripts.zip

Hi,

Please note STANAG3350 video is supplied as a component RGB signal.

So according to that configure the PRIM_MODE[3:0] (0x05) & VID_STD[3:0] (0x06) registers.

42 05 01 ; PRIM_MODE = 001b COMP - "using component input, we can send either YPbPr or analog RGB". 

Also please refer this FAQ to know about the things that need to taken care for generating the interrupt https://ez.analog.com/video/w/documents/714/how-to-program-an-interrupt-to-tell-if-the-adv7182-adv728x-has-locked-or-lost-locked

Thanks,

Poornima

Hi Poornima,

As you have suggested we tried configuring PRIM_MODE = 001b COMP, but no video was coming out of chip.
If we select PRIM_MODE as COMP(Component video) then we dont have option to select resolution as per our requirement.
That is NTSC(720x240i) and PAL(720x288i). There is only support for progressive video.

For interrupt configuration we have followed the link that you have shared. We have configured the same way, but when we use the script5 that we had shared previously, we are not getting interrupt.

Thanks and Regards,
Gladson

Hi,

STANAG3350 video is supplied as a component RGB signal, that is the reason we told you to configure the PRIM_MODE register as 'COMP'.

Please make sure with following things for configuring the interrupt (INT1),

IO Map 0x40 0xE1  ( Active until Cleared, Drive low when active)
1) Unmask required bits.
2) Clear the interrupt.
3) Wait for interrupt to occur.
4) Once interrupt occurs the STATUS bit will go high. The RAW bit will also go high while the event occurs. The Interrupt pin (INT1) will also become active.
5) The interrupt should be then cleared.

Also Please ensure that you have correctly configured the interrupt - Our interrupts are open drain by default which requires a pull up resistor external to the part. The interrupt can also be configured as "drives low when active" or "drives high when active".

Thanks,

Poornima

Hi Poornima,

We have tried configuring interrupt exactly same as you had suggested.
IO Map 0x40 0xE1 ( Active until Cleared, Drive low when active)
But we are not getting interrupt before loading the script itself.

When we configured interrupt to drive high when active, we were able to get interrupt.
But when we execute script5 we are not getting interrupt.

To solve colour issue, we have checked configuring PRIM_MODE = 001b COMP - "using component input, we can send either YPbPr or analog RGB".
Nothing worked for us.

Why we are getting that yellow vertical line for that set of configuration?
Why we are not getting interrupt after executing that script5?
Please do review the script that we have sent and let us know.

Thanks and Regards,
Gladson

Hi,

 If it is your own system could you make sure that there are no strong pull-up on the line or that the backend processor is not somehow preventing the interrupt pin driving low.

 If there is no crystal input connected, then the INTRQ pin remaining high is expected behavior (especially if there is a pull-up resistor on this line). 

 Note:

1) Manual interrupt mode is a test mode to test the functionality of an interrupt. it is only used during ATE testing.  It is not needed by customers.
2) The manual interrupt mode is not needed by customers. It was decided to remove the write in order not to confuse customers.
3) The "SD_LOCK and SD_UNLOCK clear bits" are actually self clearing. The extra write to set the clear bits back to zero are not needed. Note that it is OK to leave this write in your software if it is already present. 

Thanks,

Poornima

Hi,

 If it is your own system could you make sure that there are no strong pull-up on the line or that the backend processor is not somehow preventing the interrupt pin driving low.

 If there is no crystal input connected, then the INTRQ pin remaining high is expected behavior (especially if there is a pull-up resistor on this line). 

 Note:

1) Manual interrupt mode is a test mode to test the functionality of an interrupt. it is only used during ATE testing.  It is not needed by customers.
2) The manual interrupt mode is not needed by customers. It was decided to remove the write in order not to confuse customers.
3) The "SD_LOCK and SD_UNLOCK clear bits" are actually self clearing. The extra write to set the clear bits back to zero are not needed. Note that it is OK to leave this write in your software if it is already present. 

Thanks,

Poornima