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ADV7403 register configuration for STANAG 3350 CLASS B/C Video Signals

Hi,


I have the following requirements for ADV7403:


I/P Video - STANAG 3350 with Sync On Green as Input to the Chip.

1)720x576i @ 50/25Hz(Class B)video resolution, Interlaced video input,RGB(STANAG Class B)
2)720x480i @ 60/30Hz(Class C)video resolution, Interlaced video input,RGB(STANAG Class C)

O/P Video - 16bit YCbCr 4:2:2 as output from the chip.

Hardware Connections:
We have custom hardware with ADV7403 chip whose input channel configuration for RGsB is given below

Ain1 - G and SOG
Ain2 - B
Ain3 - R

Could you please provide the Script for the above configurations?

Also could you please let me know the values to be set for PRIM_MODE, INSEL, SDM_SEL, and VID_STD for the above configurations?

I want to know how to configure ADV7403 to accept RGsB at Ain1, Ain2, and Ain3? What should be the channel settings for the same?

Waiting for a quick response since it is very critical for us to proceed further.

Thank you.

Parents
  • Hi,

      Please refer this configuration script  " ##SCART RGB## "(:SCART RGB IN In Thru CP YPrPb 2X1  8Bit 422 Out through Encoder)  in that don't use CVBS connection in the AIN pin and follow the remaining configuration w.r.t reference script

     SOG register related configuration are provided in ADV7403 manual & adjust the sync slicer to use SOG.

     Also use registers 0xC3 & 0XC4 for configuring the AIN1,AIN2,AIN3 and crosscheck this configuration(ADC SWITCH) in Page 277.

    Thanks,

    Poornima

  • Hi,

    Thank you for your response.

    I want to understand, If I use Ain1, Ain2, and Ain3 using C3 and C4 registers, how ADV7403 understands that Ain1 is G, Ain2 is B and Ain3 is R? With the script given, is it possible that the Chip will recognize Ain1 as G, Ain2 as B and Ain3 as R? Is there any specific settings to be done in order to give RGB properly to the chip?

    Thank you.

  • Hi,

      Please note freerun nothing but "Receiver enters free run only when the TMDS clock is not detected or when the detected input format does not match the format indicated by the PRIM_MODE [3:0] and VID_STD [5:0] settings.
       For example, if input video is not present. It controls the default color insertion and causes the receiver to generate a default clock.

     If your facing issue with general PAL input & PAL output, then you need to crosscheck your schematic.

    Thanks,

    Poornima

  • Hello,

    Thank you for the quick response

    Will check and let you know regarding the free running mode

    Would like to know the following information:-

    (1) "the number of pixels between SAV and EAV should have been 720, where as here it is 1440"

    Is there any other register need to be taken care for this ?

    (2) In case of STANAG input, we can observe blur output and more blue color component in the output

    Is this because of CSC registers? or should i need to configure the offset registers for the three channels

    (3) In case of STANAG input :- I am able to get the output 8-bit YCrCb 4:2:2 in Component processor with DDR mode, but my requirement is to work with SDR mode, so I wanted to know whether this is possible or not?

    Thanks & Regards,

    Arpitha

  • Hi,

    (1) "the number of pixels between SAV and EAV should have been 720, where as here it is 1440"

    Is there any other register need to be taken care for this ?

       Generally we will use the 'PRIM_MODE and VID_STD' registers are setting the free run mode & leave these configuration.

    (3) In case of STANAG input :- I am able to get the output 8-bit YCrCb 4:2:2 in Component processor with DDR mode, but my requirement is to work with SDR mode, so I wanted to know whether this is possible or not?

    For 8bit 422 SDR mode, Please make sure with below things,
            42 6B 83 ; 422 8bit out
            42 C9 00 ; SDR mode
            42 52 00 ; Colour Space Conversion from RGB->YCrCb
    As per CPOP_SEL[0:3] register configuration,if it is 83 then it will be like 16bit output, So for 8 bit output we need to configure the pixel port in below pin assignment.

       8-bit  out       YPrPb=P19-P12/P2-P9.
      16-bit out       Y= P19-P12
                              PrPb = P2-P9.

    Thanks,

    Poornima

  • Hello,

    I tried with this following configuration:-

    For 8bit 422 SDR mode,
            42 6B 83 ; 422 8bit out
            42 C9 00 ; SDR mode
            42 52 00 ; Color Space Conversion from RGB->YCrCb

     8-bit  out:- YPrPb =P19-P12

    But ,not able to get the output in the SDR mode

    I suspect because of the DDR mode the wordings are not clear because with the initial configuration where i used to get black and white output the output video was clear, only color issue was faced

    Any suggestion, where any ADI settings has to be followed for the registers where the output from the decoder is 8-bit YCrCb 422 in SDR mode when the input is STANAG.

    Thanks & Regards,

    Arpitha

  • Hi,

      We basically have no scripts or support for STANAG 3350 although if you search the forums you will see several threads with suggestions for custom formats. We don't test the format or have any way to test it so what you can find on the forum is all we have to offer for STANAG 3350.

     Please note according to specification,we can configure the SDR output in below ways ,

    Composite and S-Video pixel data output modes:
       - 8-/10-bit ITU-R BT.656 4:2:2 YCrCb with embedded time codes and/or HS, VS
    and FIELD.
      - 16-/20-bit YCrCb with embedded time codes and/or HS, VS and FIELD.

    Component pixel data output modes:
    - Single data rate (SDR) 8-/10-bit 4:2:2 YCrCb for 525i and 625i
    - SDR 16-/20-bit 4:2:2 YCrCb for all standards
    - Double data rate (DDR) 8-/10-bit 4:2:2 YCrCb
    - DDR 12-bit 4:4:4 RGB

    Thanks,

    Poornima

  • Hello,

    Thank you for the support

    Following are the observation when done changes with the script:-

    (1)When used the script recommended by ADI (from ADV7181C_RGB_SOG.pdf)  tried to debug the 8-bit data from the decoder by capturing it in the FPGA with the help of debug probes inside the FPGA, observation was the data is sent from the decoder in SDR mode (in BT.656 format) where, the 0xC9 register was configured to 0x0C (DDR mode)

    What is the 8-bit DDR mode LLC frequency?

    (2)When the 0xC9 register is configured to 0x00 (SDR mode), the 8-bit data is not sent in BT.656 format

    (3)We checked the CP AV control register and CP default color force register and the default color registers to get at-least the free run output, tried with forcing the default color to be blue but at the output we get a combination of all three colors(red, blue and green)

    Can you suggest what can be cross checked either register setting or which part of schematic to get proper output 

    Thanks & Regards,

    Arpitha

  • Hi,

     As stated above, SDR 8-/10-bit ITU-R BT.656 4:2:2 YCrCb is only possible when the ADV7181C input is Composite and S-Video.

    For blue color output, Please configure the 0xBF(CP DEF COL) register as "0x02".

    Thanks,

    Poornima

  • Hello,

    Wanted to know what is the 8-bit DDR mode LLC frequency in CP mode?

    Thanks & Regards,

    Arpitha

  • Hi,

      DDR mode nothing but the pixel output port can be configured in an 8-/10-/12-bit 4:2:2 YCrCb upto a clock rate of 75Mhz (i.e In DDR mode we can support maximum clock rate upto 75MHz.

      Please note DDR mode doesn't change the overall performance of the part-- DDR mode maximum would be half the SDR mode maximum.  It's really no different than SDR mode-- just half the pixel clock rate since you are getting pixels on each edge instead of every other edge. 

       

    Note: DDR mode, a new data value is presented on the positive and the negative edge of the
    LLC (line-locked clock) and, hence double the amount of data is transferred.

    Thanks,

    Poornima

  • Hello,

    Wanted to know what is the DDR mode maximum and SDR mode maximum?

    Thanks,

    Arpitha

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