ADV7403 register configuration for STANAG 3350 CLASS B/C Video Signals

Hi,

  Please refer this configuration script  " ##SCART RGB## "(:SCART RGB IN In Thru CP YPrPb 2X1  8Bit 422 Out through Encoder)  in that don't use CVBS connection in the AIN pin and follow the remaining configuration w.r.t reference script

 SOG register related configuration are provided in ADV7403 manual & adjust the sync slicer to use SOG.

 Also use registers 0xC3 & 0XC4 for configuring the AIN1,AIN2,AIN3 and crosscheck this configuration(ADC SWITCH) in Page 277.

Thanks,

Poornima

Hi,

Thank you for your response.

I want to understand, If I use Ain1, Ain2, and Ain3 using C3 and C4 registers, how ADV7403 understands that Ain1 is G, Ain2 is B and Ain3 is R? With the script given, is it possible that the Chip will recognize Ain1 as G, Ain2 as B and Ain3 as R? Is there any specific settings to be done in order to give RGB properly to the chip?

Thank you.

Hello,

When we tapped the 8-bit output signal from the decoder, what we observed is irrespective of any color test pattern input to the decoder, the values of Y,Cb,Cr will be in the range of white ,black, grey color values

which is the reason why we get the black and white output, which indicates CSC is not enabled in the decoder

Request you to go through the configuration script attached in the above reply and please let us know soon if there is any mistake in the configuration

Thanks & Regards

Arpitha

Hi,

  Please refer below comments,

     1.Please remove INSEL configuration(i.e 0x00) register. The settings of INSEL and the manual input muxing registers (ADC0/1/2/3_SW) are contradict to each other, so when ADC0/1/2/3_sw settings are used we can ignore the INSEL configuration.

        Please configure AIN 4,5,6 as like below

               42 C3 46 ; ADC1 to Ain4, ADC0 to Ain6,
               42 C4 B5 ; ADC2 to Ain5
                   or
              42 C3 56 ; ADC1 to Ain5, ADC0 to Ain6,
              42 C4 B4 ; ADC2 to Ain4

     2. Please configure the CSC register as like below

42 52 00 ; Colour Space Conversion from RGB->YCrCb
42 53 00 ; CSC
42 54 12 ; CSC
42 55 90 ; CSC
42 56 38 ; CSC
42 57 69 ; CSC
42 58 48 ; CSC
42 59 08 ; CSC
42 5A 00 ; CSC
42 5B 75 ; CSC
42 5C 21 ; CSC
42 5D 00 ; CSC
42 5E 1A ; CSC
42 5F B8 ; CSC
42 60 08 ; CSC
42 61 00 ; CSC
42 62 20 ; CSC
42 63 03 ; CSC
42 64 D7 ; CSC
42 65 19 ; CSC
42 66 48 ; CSC last
42 67 13 ; DPP Filters

    3.  Please configure the PRIM_MODE and VID_STD to the nearest available standard to correctly configure the internal parameters  of the CP core to decode the specific SD/HD/GR and Interlace/Progressive standard.

  4.  Please remove below configuration.        
                 {0x42, 0X0B, 0X00},//ADV7181C Hue register
                 {0x42, 0X08, 0X80},//ADV7181C contrast register
                 {0x42, 0X0A, 0X80},//ADV7181C Brightness

Thanks,

Poornima

Hello,

Thank you for the response.

I followed the comments shared by you.

observation is:- 

Green test pattern is observed in the display (when 0x05 = 0x01 and 0x06 = 0x02/0x00)

when the registers are updated the Status register 0x12 is read, the value is 0xC0, which indicates CP free running is enabled, 

In our case the STANAG input is 720 * 575 @25i RGB so according to the manual we need to configure the 0x05= 0x02, which fails to work

Updated register configuration is attached, could you please check it once again whether the required registers are configured or is there any sequence of the register configuration to be followed ,like is there any sequence mismatch in the registers configured.

Thanks & Regards,

Arpitha

{0x42,0x01,0xC8},//video selection
{0x42,0x02,0x04},//reserved
{0x42,0X04,0X45},//extended op control
{0x42,0x05,0x01},//YPrPb component
{0x42,0x06,0x02},//YPrPb component
{0x42,0x0C,0x36},
{0x42,0x0D,0x7C},
{0x42, 0X1D, 0X47},//Enable 28MHz Crystal
{0x42, 0X27, 0X98},//Swap Cr & Cb & YC Delay Correction
{0x42, 0X31, 0X02},//Clears NEWAV_MODE, SAV/EAV  to suit ADV video encoders
{0x42, 0X3A, 0X10},//set latch clock settings to 001b
{0x42, 0X3B, 0X81},//Enable internal Bias
{0x42, 0x3C, 0x5B},//sog AND pll(>22)
{0x42, 0XF3, 0X07},// Enable Anti Alias Filters on ADC 0,1,2
{0x42, 0XF9, 0X03},//VS Mode Control
{0x42, 0X0E, 0X80},//ADI Recommended Setting
{0x42, 0X52, 0X00},
{0x42, 0X53, 0X00},
{0x42, 0X54, 0X12},
{0x42, 0X55, 0x90},
{0x42, 0X56, 0X38},
{0x42, 0X57, 0X69},
{0x42, 0X58, 0X48},
{0x42, 0X59, 0X08},
{0x42, 0X5A, 0X00},
{0x42, 0X5B, 0X75},
{0x42, 0X5C, 0X21},
{0x42, 0X5D, 0X00},
{0x42, 0X5E, 0X1A},
{0x42, 0X60, 0X08},
{0x42, 0X61, 0X00},
{0x42, 0X62, 0X20},
{0x42, 0X63, 0X03},
{0x42, 0X64, 0XD7},
{0x42, 0X65, 0X19},//0x39
{0x42, 0X66, 0X48},
{0x42, 0X67, 0X13},//DPP Filters
{0x42, 0X68, 0X01},//automatic selection od DOO_FILT
{0x42, 0X69, 0XA0},//
{0x42, 0X6B, 0XC3},// 422 8bit out and DE and field selection
{0x42, 0X73, 0XD0},//Enable Manual Gain and set CH_A gain
{0x42, 0X74, 0X04},//Set CH_A and CH_B Gain
{0x42, 0X75, 0X01},//Set CH_B and CH_C Gain
{0x42, 0X76, 0X00},//Set CH_C Gain
{0x42, 0x77, 0x00},
{0x42, 0x78, 0x08},
{0x42, 0x79, 0xAE},
{0x42, 0x7A, 0x0F},
{0x42, 0x84, 0x0C},//No Filtering
{0x42, 0x85, 0x18},//Autodetect mode for sync source
{0x42, 0X86, 0X0B},//[4]:- Swap Cr and Cb
{0x42, 0x87, 0xE6},//CP TLLC CONTROL 1//20
{0x42, 0x88, 0xC0},//CP TLLC CONTROL 2//for 27MHz (PLL divisor is 1728)
{0x42, 0x89, 0x08},//inversion of Cb and Cr in SDp mode
{0x42, 0x8A, 0x10},//VCO range
{0x42, 0x8F, 0x02},// Set FR_LL = 720
{0x42, 0X90, 0XD0},// Set FR_LL = 720
{0x42, 0X7F, 0XFF},//brightness
{0x42, 0X91, 0X50},//DPP_CP_64
{0x42, 0X0E, 0X00},//ADI Recommended Setting
{0x42, 0xBE, 0xE0},
{0x42, 0XC3, 0X56},
{0x42, 0XC4, 0XB4},//ADC3
{0x42, 0XC9, 0X00},// SDR mode

Hello,

I configured the primary mode and video standard registers, according to the value specified in the ADV7181Cmanual,

Primary mode :- 0x05 :- 0x00 (SD-M)

Video Standard :- 0x06 :- 0x0B ( CP processor 720*576 @625i)

Observation is whenever the video standard is configured, the status is CP free running mode ( verified by reading 0x12 register i.e. 0x12 = 0xC0) 

When the LLC clock is probed it is 27MHz,

Request you to please let me know soon is there any registers need to be taken care or is there any mismatch in the I2C sequence

Thanks & Regards,

Arpitha

Hello,

I changed some of the register set configuration, and with the script attached here, The valid signal is detected and the status is 0x80 when 0x12 register is read

Output observation is overlay of green and pink color.

Is this overlay because of some CSC registers or is it because of the settings on primary mode and video standard?

{0x42, 0x01, 0xC8},//video selection
{0x42, 0x02, 0x04},//reserved
{0x42, 0X04, 0X45},//extended op control
{0x42, 0x05, 0x01},//YPrPb component
{0x42, 0x06, 0x01},//YPrPb component//1440
{0x42, 0x13, 0x04},
{0x42, 0x0C, 0x36},
{0x42, 0X0E, 0X00},
{0x42, 0X1D, 0X47},//Enable 28MHz Crystal
{0x42, 0X27, 0X58},//Swap Cr & Cb & YC Delay Correction
{0x42, 0X31, 0X02},//Clears NEWAV_MODE, SAV/EAV  to suit ADV video encoders
{0x42, 0X3A, 0X11},//set latch clock settings to 001b
{0x42, 0X3B, 0X85},//Enable internal Bias//81
{0x42, 0x3C, 0x5B},//sog AND pll(>22)
{0x42, 0XC3, 0X56},
{0x42, 0XC4, 0XB4},//ADC3
{0x42, 0XF3, 0X07},// Enable Anti Alias Filters on ADC 0,1,2
{0x42, 0XF9, 0X03},//VS Mode Control
{0x42, 0X52, 0X00},
{0x42, 0X53, 0X00},
{0x42, 0X54, 0X12},
{0x42, 0X55, 0x90},
{0x42, 0X56, 0X38},
{0x42, 0X57, 0X69},
{0x42, 0X58, 0X48},
{0x42, 0X59, 0X08},
{0x42, 0X5A, 0X00},
{0x42, 0X5B, 0X75},
{0x42, 0X5C, 0X21},
{0x42, 0X5D, 0X00},
{0x42, 0X5E, 0X1A},
{0x42, 0x5F, 0xB8},//
{0x42, 0X60, 0X08},
{0x42, 0X61, 0X00},
{0x42, 0X62, 0X20},
{0x42, 0X63, 0X03},
{0x42, 0X64, 0XD7},
{0x42, 0X65, 0X19},//0x39
{0x42, 0X66, 0X48},
{0x42, 0X67, 0X13},//DPP Filters
{0x42, 0X68, 0X01},//automatic selection od DOO_FILT
{0x42, 0X69, 0X00},//
{0x42, 0X6A, 0X00},
{0x42, 0X6B, 0XC3},// 422 8bit out and DE and field selection
{0x42, 0X73, 0XD0},//Enable Manual Gain and set CH_A gain
{0x42, 0X74, 0X04},//Set CH_A and CH_B Gain
{0x42, 0X75, 0X01},//Set CH_B and CH_C Gain
{0x42, 0X76, 0X00},//Set CH_C Gain
{0x42, 0x77, 0x02},
{0x42, 0x78, 0x08},
{0x42, 0x79, 0x02},
{0x42, 0x7A, 0x00},
{0x42, 0X7B, 0X1F},
{0x42, 0X7D, 0X8C},
{0x42, 0X7E, 0X8C},
{0x42, 0X7F, 0XFF},//brightness
{0x42, 0X86, 0X0B},//[4]:- Swap Cr and Cb
{0x42, 0XF3, 0X07},// Enable Anti Alias Filters on ADC 0,1,2
{0x42, 0XF4, 0X3F},
{0x42, 0XF9, 0X03},//VS Mode Control
{0x42, 0XF4, 0X1D},
{0x42, 0x89, 0x08},//inversion of Cb and Cr in SDp mode
{0x42, 0x8A, 0x10},//VCO range
{0x42, 0x8F, 0x00},// Set FR_LL = 720
{0x42, 0X90, 0X00},// Set FR_LL = 720

Thanks & Regards

Arpitha

Hi,

 Please let us know, Have you configured the below registers without doing any register configuration.

    Format - 720*576 @625i

42 05 00 ; Prim_Mode =000b for SD-M
42 06 0B ; VID_STD=1011 for SD  4x1 625i
42 1D 47 ; Enable 28MHz Crystal
42 3A 11 ; Set Latch Clock 01b, Power Down ADC3
42 3B 81 ; Enable internal Bias
42 3C 52 ; PLL_QPUMP to 010b
42 C4 85 ; Manual Muxing - ADC2=AIN5(R)
42 C3 46 ; Manual Muxing - ADC0=AIN6(G), ADC1=AIN4(B)
42 52 00 ; Colour Space Conversion from RGB->YCrCb
42 53 00 ; CSC
42 54 12 ; CSC
42 55 90 ; CSC
42 56 38 ; CSC
42 57 69 ; CSC
42 58 48 ; CSC
42 59 08 ; CSC
42 5A 00 ; CSC
42 5B 75 ; CSC
42 5C 21 ; CSC
42 5D 00 ; CSC
42 5E 1A ; CSC
42 5F B8 ; CSC
42 60 08 ; CSC
42 61 00 ; CSC
42 62 20 ; CSC
42 63 03 ; CSC
42 64 D7 ; CSC
42 65 19 ; CSC
42 66 48 ; CSC last
42 67 13 ; DPP Filters
42 6B C3 ; Select 422 8 bit YPrPb out from CP
42 73 CF ; Enable Manual Gain and set CH_A gain
42 74 A3 ; Set CH_A and CH_B Gain - 0FAh
42 75 E8 ; Set CH_B and CH_C Gain
42 76 FA ; Set CH_C Gain
42 7B 06 ; clears the bits CP_DUP_AV and AV_Blank_EN
42 85 19 ; Turn off SSPD and force SOY. For Eval Board.
42 86 1B ; Enable stdi_line_count_mode
42 8F 77 ; FR_LL to 1820 & Enable 28.63MHz LLC
42 90 1C ; FR_LL to 1820
42 BF 06 ; Blue Screen Free Run Colour
42 C0 40 ; default color
42 C1 F0 ; default color
42 C2 80 ; Default color
42 C5 01 ; CP_CLAMP_AVG_FACTOR[1-0] = 00b
42 C9 0C ; Enable DDR Mode
42 F3 07 ; Enable Anti Alias Filters on ADC 0,1,2
42 0E 80 ; ADI Recommended Setting
42 52 46 ; ADI Recommended Setting
42 54 00 ; ADI Recommended Setting
42 F6 3B ; ADI Recommended Setting
42 0E 00 ; ADI Recommended Setting

Thanks,

Poornima

Hello,

Thank you for the script

Following are the observations:-

Test case 1:-

When I configured all the register with same value mentioned in the above script ,except the 0xC9 to 0x00 (because we need it in SDR mode)

Here the status is CP is in free running mode

Test case 2:-

When I configure all the registers as mentioned above I get a colored output (far better then before but not a cleared one), but in this case the chip is configured to DDR mode, where as we need it in SDR mode

Please find the attached image of the screen output which has to be blue test pattern when no input is connected, but it shows shades of blue and green

Thanks & Regards,

Arpitha

Hello,

One observation is with the script shared , the number of pixels between SAV and EAV should have been 720, where as here it is 1440 

But according to the register configuration of primary mode and video standard, it has to be 720 pixels

Primary mode :- 0x05 :- 0x00 (SD-M)

Video Standard :- 0x06 :- 0x0B ( CP processor 720*576 @625i)

Is there any other register need to be taken care for this

Thanks & Regards,

Arpitha

Hi,

  Please let us know your Rx & Tx chip in your board.

   Let me clarify few things from your end.

  Please let me know, you are not even getting the freerun output properly?

If So,Please refer ADV7180 RSD document ADV7180_RSD.pdf  pg 10 section 3.3 for free run mode which is available at ADV7180 Design Support Files
The writes below force the ADV7180 into free-run mode. The writes must be made in the order shown below and should be performed after an Analog Devices’ recommended script. User Map
       42 0C 37  Force Free-Run mode
       42 00 XX  Force Video Standard1
       42 0D YY  Set Color Output2
-  Have you tried with general PAL/NTSC input instead of STANAG ?

Thanks,

Poornima

Hello,

Thank you for the response

The RX chip is ADV7181C and the TX chip is ADV7343

In case of STANAG input and PAL output the free run output is like the one attached in the previous reply

In case of PAL input and the PAL output , the free run output is attached below

...

Thanks & Regards,

Arpitha

Hello,

Thank you for the response

The RX chip is ADV7181C and the TX chip is ADV7343

In case of STANAG input and PAL output the free run output is like the one attached in the previous reply

In case of PAL input and the PAL output , the free run output is attached below

...

Thanks & Regards,

Arpitha

Hi,

  Please note freerun nothing but "Receiver enters free run only when the TMDS clock is not detected or when the detected input format does not match the format indicated by the PRIM_MODE [3:0] and VID_STD [5:0] settings.
   For example, if input video is not present. It controls the default color insertion and causes the receiver to generate a default clock.

 If your facing issue with general PAL input & PAL output, then you need to crosscheck your schematic.

Thanks,

Poornima

Hello,

Thank you for the quick response

Will check and let you know regarding the free running mode

Would like to know the following information:-

(1) "the number of pixels between SAV and EAV should have been 720, where as here it is 1440"

Is there any other register need to be taken care for this ?

(2) In case of STANAG input, we can observe blur output and more blue color component in the output

Is this because of CSC registers? or should i need to configure the offset registers for the three channels

(3) In case of STANAG input :- I am able to get the output 8-bit YCrCb 4:2:2 in Component processor with DDR mode, but my requirement is to work with SDR mode, so I wanted to know whether this is possible or not?

Thanks & Regards,

Arpitha

Hi,

(1) "the number of pixels between SAV and EAV should have been 720, where as here it is 1440"

Is there any other register need to be taken care for this ?

   Generally we will use the 'PRIM_MODE and VID_STD' registers are setting the free run mode & leave these configuration.

(3) In case of STANAG input :- I am able to get the output 8-bit YCrCb 4:2:2 in Component processor with DDR mode, but my requirement is to work with SDR mode, so I wanted to know whether this is possible or not?

For 8bit 422 SDR mode, Please make sure with below things,
        42 6B 83 ; 422 8bit out
        42 C9 00 ; SDR mode
        42 52 00 ; Colour Space Conversion from RGB->YCrCb
As per CPOP_SEL[0:3] register configuration,if it is 83 then it will be like 16bit output, So for 8 bit output we need to configure the pixel port in below pin assignment.

   8-bit  out       YPrPb=P19-P12/P2-P9.
  16-bit out       Y= P19-P12
                          PrPb = P2-P9.

Thanks,

Poornima

Hello,

I tried with this following configuration:-

For 8bit 422 SDR mode,
        42 6B 83 ; 422 8bit out
        42 C9 00 ; SDR mode
        42 52 00 ; Color Space Conversion from RGB->YCrCb

 8-bit  out:- YPrPb =P19-P12

But ,not able to get the output in the SDR mode

I suspect because of the DDR mode the wordings are not clear because with the initial configuration where i used to get black and white output the output video was clear, only color issue was faced

Any suggestion, where any ADI settings has to be followed for the registers where the output from the decoder is 8-bit YCrCb 422 in SDR mode when the input is STANAG.

Thanks & Regards,

Arpitha

Hi,

  We basically have no scripts or support for STANAG 3350 although if you search the forums you will see several threads with suggestions for custom formats. We don't test the format or have any way to test it so what you can find on the forum is all we have to offer for STANAG 3350.

 Please note according to specification,we can configure the SDR output in below ways ,

Composite and S-Video pixel data output modes:
   - 8-/10-bit ITU-R BT.656 4:2:2 YCrCb with embedded time codes and/or HS, VS
and FIELD.
  - 16-/20-bit YCrCb with embedded time codes and/or HS, VS and FIELD.

Component pixel data output modes:
- Single data rate (SDR) 8-/10-bit 4:2:2 YCrCb for 525i and 625i
- SDR 16-/20-bit 4:2:2 YCrCb for all standards
- Double data rate (DDR) 8-/10-bit 4:2:2 YCrCb
- DDR 12-bit 4:4:4 RGB

Thanks,

Poornima

Hello,

Thank you for the support

Following are the observation when done changes with the script:-

(1)When used the script recommended by ADI (from ADV7181C_RGB_SOG.pdf)  tried to debug the 8-bit data from the decoder by capturing it in the FPGA with the help of debug probes inside the FPGA, observation was the data is sent from the decoder in SDR mode (in BT.656 format) where, the 0xC9 register was configured to 0x0C (DDR mode)

What is the 8-bit DDR mode LLC frequency?

(2)When the 0xC9 register is configured to 0x00 (SDR mode), the 8-bit data is not sent in BT.656 format

(3)We checked the CP AV control register and CP default color force register and the default color registers to get at-least the free run output, tried with forcing the default color to be blue but at the output we get a combination of all three colors(red, blue and green)

Can you suggest what can be cross checked either register setting or which part of schematic to get proper output 

Thanks & Regards,

Arpitha

Hi,

 As stated above, SDR 8-/10-bit ITU-R BT.656 4:2:2 YCrCb is only possible when the ADV7181C input is Composite and S-Video.

For blue color output, Please configure the 0xBF(CP DEF COL) register as "0x02".

Thanks,

Poornima

Hello,

Wanted to know what is the 8-bit DDR mode LLC frequency in CP mode?

Thanks & Regards,

Arpitha

Hi,

  DDR mode nothing but the pixel output port can be configured in an 8-/10-/12-bit 4:2:2 YCrCb upto a clock rate of 75Mhz (i.e In DDR mode we can support maximum clock rate upto 75MHz.

  Please note DDR mode doesn't change the overall performance of the part-- DDR mode maximum would be half the SDR mode maximum.  It's really no different than SDR mode-- just half the pixel clock rate since you are getting pixels on each edge instead of every other edge. 

Note: DDR mode, a new data value is presented on the positive and the negative edge of the
LLC (line-locked clock) and, hence double the amount of data is transferred.

Thanks,

Poornima

Hello,

Wanted to know what is the DDR mode maximum and SDR mode maximum?

Thanks,

Arpitha