ADV7403 register configuration for STANAG 3350 CLASS B/C Video Signals

Hi,

  Please refer this configuration script  " ##SCART RGB## "(:SCART RGB IN In Thru CP YPrPb 2X1  8Bit 422 Out through Encoder)  in that don't use CVBS connection in the AIN pin and follow the remaining configuration w.r.t reference script

 SOG register related configuration are provided in ADV7403 manual & adjust the sync slicer to use SOG.

 Also use registers 0xC3 & 0XC4 for configuring the AIN1,AIN2,AIN3 and crosscheck this configuration(ADC SWITCH) in Page 277.

Thanks,

Poornima

Hi,

Thank you for your response.

I want to understand, If I use Ain1, Ain2, and Ain3 using C3 and C4 registers, how ADV7403 understands that Ain1 is G, Ain2 is B and Ain3 is R? With the script given, is it possible that the Chip will recognize Ain1 as G, Ain2 as B and Ain3 as R? Is there any specific settings to be done in order to give RGB properly to the chip?

Thank you.

Hi,

  "The analog input muxes of the ADV7403 must be controlled directly. This is referred to as manual input muxing.     The manual muxing is activated by setting the ADC_SWITCH_MAN bit. It only affects the analog switches in front of the ADCs.

Please note PRIM_MODE and VID_STD still have to be set so that the follow on blocks process the video data in the correct format." 

Refer below configuration for 0xC3 & 0xC4 for processing the RGB inputs using AIN pins.

  Ain1 as G    ADC0_SW[3:0]  0xc3   -  0001
  Ain2 as B    ADC2_SW [3:0] 0xC4   -  0010
  Ain3 as R    ADC1_SW [3:0] 0xc3  -    0011

Note:  The manual muxing is activated by setting the ADC_SW_MAN_EN bits. It only affects the analogue switches in front of the ADCs. PRIM_MODE and VID_STD still have to be set so the follow-on blocks process the video data in the correct format. Which means: If the settings of INSEL and the manual input muxing registers (ADC0/1/2/3_SW) contradict each other, the ADC0/1/2/3_sw settings apply and INSEL is ignored. For more details please refer Page 19 in ADV7403 manual.

Thanks,

Poornima

Hi,

Thank you for your reply.

I am able to detect the output from ADV7403, confirmed the detection using Status register 0x12[6].

But I have some questions regarding the output.

In my case, the PRIM_MODE will be set to SD? Can you please let me know the values for PRIM_MODE and VID_STD in my case.

If I need the output in BT.656 format, should I set any other register values?
 
I wanted to confirm whether the output whatever I am able to capture with the given script is in BT.656 format.

Can I use any other status registers to confirm the output data format? 

Thank you.

Hi,

   Generally PRIM_MODE and VID_STD are used to set up the free run modes.These controls are used to specify the free run output standard. Please refer table 12 in ADV7403 manual for setting the PRIM_MODE and VID_STD based upon your formats.

 Regarding BT.656 output, Please configure the OF_SEL[3:0] register for BT.656 setting & refer below snap for your reference,
     

Thanks,

Poornima

Hello Poornima,

Thank you for your reply.

I am able to get the output in the BT.656 format. But there is a greenish tint on the output as in the below image.

As you can see in the above image, there is a green colour issue with the image.

Can you please suggest any changes to the register values to remove this greenish tint on the output?

I tried a couple of CSC registers, but the same issue exists. 

Thank you.

Hi,

 Please ensure 0x86 register value as 0x0B - "42 86 0B".

Thanks,

Poornima

Hello,

Thank you for your input.

I have checked the register 0x86, it is set for 0x0B. 

Thank you.

Hi,

  If Possible, Could you please share your register configuration.

Thanks,

Poornima

Hi,

I have attached the register set used .

Please go through it and let me know any changes to be done.

Thank you.

XLSX

Hi,

  Please configure the CSC registers as like below configuration,

0x52 0x00 Conversion from RGB -> YPbPr
0x53 0x00 CSC Start
0x54 0x07 CSC Register
0x55 0x0C CSC Register
0x56 0x99 CSC Register
0x57 0xA9 CSC Register
0x58 0x71 CSC Register
0x59 0x08 CSC Register
0x5A 0x00 CSC Register
0x5B 0x20 CSC Register
0x5C 0xA7 CSC Register
0x5D 0xA9 CSC Register
0x5E 0x1A CSC Register
0x5F 0x8F CSC Register
0x60 0x08 CSC Register
0x61 0x00 CSC Register
0x62 0x7A CSC Register
0x63 0xE1 CSC Register
0x64 0x05 CSC Register
0x65 0x39 CSC Register
0x66 0x1F CSC last
0x73 0xD0 Enable Manual Gain and set CH_A gain
0x74 0x04 Set CH_A and CH_B Gain
0x75 0x01 Set CH_B and CH_C Gain
0x76 0x00 Set CH_C Gain

Thanks,

Poornima

Hi,

  Please configure the CSC registers as like below configuration,

0x52 0x00 Conversion from RGB -> YPbPr
0x53 0x00 CSC Start
0x54 0x07 CSC Register
0x55 0x0C CSC Register
0x56 0x99 CSC Register
0x57 0xA9 CSC Register
0x58 0x71 CSC Register
0x59 0x08 CSC Register
0x5A 0x00 CSC Register
0x5B 0x20 CSC Register
0x5C 0xA7 CSC Register
0x5D 0xA9 CSC Register
0x5E 0x1A CSC Register
0x5F 0x8F CSC Register
0x60 0x08 CSC Register
0x61 0x00 CSC Register
0x62 0x7A CSC Register
0x63 0xE1 CSC Register
0x64 0x05 CSC Register
0x65 0x39 CSC Register
0x66 0x1F CSC last
0x73 0xD0 Enable Manual Gain and set CH_A gain
0x74 0x04 Set CH_A and CH_B Gain
0x75 0x01 Set CH_B and CH_C Gain
0x76 0x00 Set CH_C Gain

Thanks,

Poornima

Hello Poornima,

Thank you for your reply.

Tried configuring the given CSC register settings along with other registers mentioned in the previous mail, but the colours are not proper as in the below image.

There is colour swapping as you can see in the above image.

Thank you.

Hi,

  Please try configuring the 0X74 ,0X75 ,0X76 ,0X77 ,0X78,0X79 , 0X7A registers as once & it seems you have been configured these registers as twice.
  Also try to swap the Cr,Cb by using register "SWPC Swap Pixel Cr/Cb (SDP), Address 0x27[7]"  & let us know.

Thanks,

Poornima

Hello,

Can I use the same CSC configuration for ADV7181C 

Thanks,

Arpitha

Hi,

  Yes, you can use the CSC configuration register which we shared above and just swap the pixel by using  "SWPC Swap Pixel Cr/Cb (SDP), Address 0x27[7]" 

Thanks,

Poornima

Hello,

I tried with the same configuration by swapping the pixel as well ,but in my case, the input is STANAG (ADV7181C)  and output is PAL/STANAG resolution from (ADV7343 IC)

When PAL input and PAL output implementation is done, the output is as expected

When STANAG input and PAL/STANAG output implementation is done ,the output video observed is black and white.

One more observation is , when the register 0x54 is configured to value 0x07 or 0x12, there is no output observed

Could you please let me know what other registers has to be taken care in case of Stanag input

Thanks & Regards,

Arpitha

Hi,

  Please make sure with STANAG3350 input like, "whether STANAG3350 video is supplied as a component RGB signal & then according to that configure the PRIM_MODE[3:0] (0x05) & VID_STD[3:0] (0x06) registers.

           42 05 01 ; PRIM_MODE = 001b COMP - "using component input, we can send either YPbPr or analog RGB". 

  Also it require by changing the PLL settings (or clamping) to sample all pixels & refer below snap for PLL recommended settings.

  http://www.analog.com/static/imported-files/application_notes/AN-0978.pdf

Thanks,

Poornima

Hello

Thank you for your response

The STANAG input to the decoder is through the following signals:- 

Ain4 - B
Ain5 - R
Ain6 - G

STANAG 3350B resolution:- 720*575 @25i 

Output format from the decoder :- 8bit YCrCb 422 in BT.656 format

8-bit out :- YCrCb :- P19-P12 pins are connected 

According to the input , I have configured the ADC switch registers and the PLL settings as described in the AN-0978 pdf 

Output image:- Black and white with patches of pink, green and blue colors and it varies

Issues:-

(1) When the primary mode register is configured to PRIM_MODE = 001b, the output  is blank with green-pink color at the bottom of the display

(2) When the VID_STD register set is configured, no output display is observed

As mentioned in  the manual "The CP circuitry is activated under the control of PRIM_MODE[3:0] and VID_STD[3:0]" but i am not able to configure these two registers, 

I have attached the registers configured for ADV7181C IC, Could you please check those register configuration and let us know which register has to be changed or to be added

		 {0x42, 0X00, 0X09},//YPrPb component
		 {0x42,0x01,0xC8},//video selection
		 {0x42,0x02,0x04},//reserved
		 {0x42, 0x3C, 0x5B},//sog AND pll(>22)
		 {0x42, 0X04, 0X45},//extended op control
		 {0x42, 0X1D, 0X47},//Enable 28MHz Crystal
		 {0x42, 0X27, 0X98},//Swap Cr & Cb & YC Delay Correction
		 {0x42, 0X6B, 0XC3},// 422 8bit out and DE and field selection
		 {0x42, 0XC9, 0X00},// SDR mode
		 {0x42, 0X31, 0X02},//Clears NEWAV_MODE, SAV/EAV  to suit ADV video encoders
		 {0x42, 0X3A, 0X10},//set latch clock settings to 001b
		 {0x42, 0X3B, 0X81},//Enable internal Bias
		 {0x42, 0X86, 0X0B},//[4]:- Swap Cr and Cb
		 {0x42, 0XC3, 0X56},//ADC 0 and ADc 1
		 {0x42, 0XC4, 0XB5},//ADC3
		 {0x42, 0XF3, 0X07},// Enable Anti Alias Filters on ADC 0,1,2
		 {0x42, 0XF9, 0X03},//VS Mode Control
		  {0x42, 0X0E, 0X80},//ADI Recommended Setting
		  {0x42, 0X52, 0X00},
		  {0x42, 0X53, 0X00},
		  {0x42, 0X54, 0X00},
		  {0x42, 0X55, 0x0C},
		  {0x42, 0X56, 0X99},
		  {0x42, 0X57, 0X69},
		  {0x42, 0X58, 0X71},
		  {0x42, 0X59, 0X08},
		  {0x42, 0X5A, 0X00},
		  {0x42, 0X5B, 0X20},
		  {0x42, 0X5C, 0XA7},
		  {0x42, 0X5D, 0XA9},
		  {0x42, 0X5E, 0X1A},
		  {0x42, 0X5F, 0X8F},
		  {0x42, 0X60, 0X08},
		  {0x42, 0X61, 0X00},
		  {0x42, 0X62, 0X7A},
		  {0x42, 0X63, 0XE1},
		  {0x42, 0X64, 0X05},
		  {0x42, 0X65, 0X19},//0x39
		  {0x42, 0X66, 0X1F},
		  {0x42, 0X67, 0X13},
		  {0x42, 0X68, 0X01},
		  {0x42, 0X73, 0XD0},//Enable Manual Gain and set CH_A gain
		  {0x42, 0X74, 0X04},//Set CH_A and CH_B Gain
		  {0x42, 0X75, 0X01},//Set CH_B and CH_C Gain
		  {0x42, 0X76, 0X00},//Set CH_C Gain
		  {0x42, 0x77, 0xFF},
		  {0x42, 0x78, 0xFF},
		  {0x42, 0x79, 0xFF},
		  {0x42, 0x7A, 0xFF},
		  {0x42, 0X0B, 0X00},//ADV7181C Hue register
		  {0x42, 0X08, 0X80},//ADV7181C contrast register
		  {0x42, 0X0A, 0X80},//ADV7181C Brightness Adjust
		  {0x42, 0x84, 0x0C},//No Filtering
		  {0x42, 0x85, 0x18},//Autodetect mode for sync source
		  {0x42, 0x87, 0xE6},//CP TLLC CONTROL 1//20
		  {0x42, 0x88, 0xC0},//CP TLLC CONTROL 2//for 27MHz (PLL divisor is 1728)
		  {0x42, 0x89, 0x08},//inversion of Cb and Cr in SDp mode
		  {0x42, 0x8A, 0x10},//VCO range
		  {0x42, 0x8F, 0x02},// Set FR_LL = 720
		  {0x42, 0X90, 0XD0},// Set FR_LL = 720
		  {0x42, 0X7F, 0XFF},//brightness
		  {0x42, 0X91, 0X50},//DPP_CP_64
		  {0x42, 0X0E, 0X00},//ADI Recommended Setting
		  {0x42, 0X0E, 0X00},//ADI Recommended Setting

Thanks & Regards,

Arpitha

Hello,

When we tapped the 8-bit output signal from the decoder, what we observed is irrespective of any color test pattern input to the decoder, the values of Y,Cb,Cr will be in the range of white ,black, grey color values

which is the reason why we get the black and white output, which indicates CSC is not enabled in the decoder

Request you to go through the configuration script attached in the above reply and please let us know soon if there is any mistake in the configuration

Thanks & Regards

Arpitha

Hi,

  Please refer below comments,

     1.Please remove INSEL configuration(i.e 0x00) register. The settings of INSEL and the manual input muxing registers (ADC0/1/2/3_SW) are contradict to each other, so when ADC0/1/2/3_sw settings are used we can ignore the INSEL configuration.

        Please configure AIN 4,5,6 as like below

               42 C3 46 ; ADC1 to Ain4, ADC0 to Ain6,
               42 C4 B5 ; ADC2 to Ain5
                   or
              42 C3 56 ; ADC1 to Ain5, ADC0 to Ain6,
              42 C4 B4 ; ADC2 to Ain4

     2. Please configure the CSC register as like below

42 52 00 ; Colour Space Conversion from RGB->YCrCb
42 53 00 ; CSC
42 54 12 ; CSC
42 55 90 ; CSC
42 56 38 ; CSC
42 57 69 ; CSC
42 58 48 ; CSC
42 59 08 ; CSC
42 5A 00 ; CSC
42 5B 75 ; CSC
42 5C 21 ; CSC
42 5D 00 ; CSC
42 5E 1A ; CSC
42 5F B8 ; CSC
42 60 08 ; CSC
42 61 00 ; CSC
42 62 20 ; CSC
42 63 03 ; CSC
42 64 D7 ; CSC
42 65 19 ; CSC
42 66 48 ; CSC last
42 67 13 ; DPP Filters

    3.  Please configure the PRIM_MODE and VID_STD to the nearest available standard to correctly configure the internal parameters  of the CP core to decode the specific SD/HD/GR and Interlace/Progressive standard.

  4.  Please remove below configuration.        
                 {0x42, 0X0B, 0X00},//ADV7181C Hue register
                 {0x42, 0X08, 0X80},//ADV7181C contrast register
                 {0x42, 0X0A, 0X80},//ADV7181C Brightness

Thanks,

Poornima

Hello,

Thank you for the response.

I followed the comments shared by you.

observation is:- 

Green test pattern is observed in the display (when 0x05 = 0x01 and 0x06 = 0x02/0x00)

when the registers are updated the Status register 0x12 is read, the value is 0xC0, which indicates CP free running is enabled, 

In our case the STANAG input is 720 * 575 @25i RGB so according to the manual we need to configure the 0x05= 0x02, which fails to work

Updated register configuration is attached, could you please check it once again whether the required registers are configured or is there any sequence of the register configuration to be followed ,like is there any sequence mismatch in the registers configured.

Thanks & Regards,

Arpitha

{0x42,0x01,0xC8},//video selection
{0x42,0x02,0x04},//reserved
{0x42,0X04,0X45},//extended op control
{0x42,0x05,0x01},//YPrPb component
{0x42,0x06,0x02},//YPrPb component
{0x42,0x0C,0x36},
{0x42,0x0D,0x7C},
{0x42, 0X1D, 0X47},//Enable 28MHz Crystal
{0x42, 0X27, 0X98},//Swap Cr & Cb & YC Delay Correction
{0x42, 0X31, 0X02},//Clears NEWAV_MODE, SAV/EAV  to suit ADV video encoders
{0x42, 0X3A, 0X10},//set latch clock settings to 001b
{0x42, 0X3B, 0X81},//Enable internal Bias
{0x42, 0x3C, 0x5B},//sog AND pll(>22)
{0x42, 0XF3, 0X07},// Enable Anti Alias Filters on ADC 0,1,2
{0x42, 0XF9, 0X03},//VS Mode Control
{0x42, 0X0E, 0X80},//ADI Recommended Setting
{0x42, 0X52, 0X00},
{0x42, 0X53, 0X00},
{0x42, 0X54, 0X12},
{0x42, 0X55, 0x90},
{0x42, 0X56, 0X38},
{0x42, 0X57, 0X69},
{0x42, 0X58, 0X48},
{0x42, 0X59, 0X08},
{0x42, 0X5A, 0X00},
{0x42, 0X5B, 0X75},
{0x42, 0X5C, 0X21},
{0x42, 0X5D, 0X00},
{0x42, 0X5E, 0X1A},
{0x42, 0X60, 0X08},
{0x42, 0X61, 0X00},
{0x42, 0X62, 0X20},
{0x42, 0X63, 0X03},
{0x42, 0X64, 0XD7},
{0x42, 0X65, 0X19},//0x39
{0x42, 0X66, 0X48},
{0x42, 0X67, 0X13},//DPP Filters
{0x42, 0X68, 0X01},//automatic selection od DOO_FILT
{0x42, 0X69, 0XA0},//
{0x42, 0X6B, 0XC3},// 422 8bit out and DE and field selection
{0x42, 0X73, 0XD0},//Enable Manual Gain and set CH_A gain
{0x42, 0X74, 0X04},//Set CH_A and CH_B Gain
{0x42, 0X75, 0X01},//Set CH_B and CH_C Gain
{0x42, 0X76, 0X00},//Set CH_C Gain
{0x42, 0x77, 0x00},
{0x42, 0x78, 0x08},
{0x42, 0x79, 0xAE},
{0x42, 0x7A, 0x0F},
{0x42, 0x84, 0x0C},//No Filtering
{0x42, 0x85, 0x18},//Autodetect mode for sync source
{0x42, 0X86, 0X0B},//[4]:- Swap Cr and Cb
{0x42, 0x87, 0xE6},//CP TLLC CONTROL 1//20
{0x42, 0x88, 0xC0},//CP TLLC CONTROL 2//for 27MHz (PLL divisor is 1728)
{0x42, 0x89, 0x08},//inversion of Cb and Cr in SDp mode
{0x42, 0x8A, 0x10},//VCO range
{0x42, 0x8F, 0x02},// Set FR_LL = 720
{0x42, 0X90, 0XD0},// Set FR_LL = 720
{0x42, 0X7F, 0XFF},//brightness
{0x42, 0X91, 0X50},//DPP_CP_64
{0x42, 0X0E, 0X00},//ADI Recommended Setting
{0x42, 0xBE, 0xE0},
{0x42, 0XC3, 0X56},
{0x42, 0XC4, 0XB4},//ADC3
{0x42, 0XC9, 0X00},// SDR mode