ADV7403 register configuration for STANAG 3350 CLASS B/C Video Signals

Hi,


I have the following requirements for ADV7403:


I/P Video - STANAG 3350 with Sync On Green as Input to the Chip.

1)720x576i @ 50/25Hz(Class B)video resolution, Interlaced video input,RGB(STANAG Class B)
2)720x480i @ 60/30Hz(Class C)video resolution, Interlaced video input,RGB(STANAG Class C)

O/P Video - 16bit YCbCr 4:2:2 as output from the chip.

Hardware Connections:
We have custom hardware with ADV7403 chip whose input channel configuration for RGsB is given below

Ain1 - G and SOG
Ain2 - B
Ain3 - R

Could you please provide the Script for the above configurations?

Also could you please let me know the values to be set for PRIM_MODE, INSEL, SDM_SEL, and VID_STD for the above configurations?

I want to know how to configure ADV7403 to accept RGsB at Ain1, Ain2, and Ain3? What should be the channel settings for the same?

Waiting for a quick response since it is very critical for us to proceed further.

Thank you.

  • 0
    •  Analog Employees 
    on Sep 14, 2021 12:42 PM

    Hi,

      Please refer this configuration script  " ##SCART RGB## "(:SCART RGB IN In Thru CP YPrPb 2X1  8Bit 422 Out through Encoder)  in that don't use CVBS connection in the AIN pin and follow the remaining configuration w.r.t reference script

     SOG register related configuration are provided in ADV7403 manual & adjust the sync slicer to use SOG.

     Also use registers 0xC3 & 0XC4 for configuring the AIN1,AIN2,AIN3 and crosscheck this configuration(ADC SWITCH) in Page 277.

    Thanks,

    Poornima

  • Hi,

    Thank you for your response.

    I want to understand, If I use Ain1, Ain2, and Ain3 using C3 and C4 registers, how ADV7403 understands that Ain1 is G, Ain2 is B and Ain3 is R? With the script given, is it possible that the Chip will recognize Ain1 as G, Ain2 as B and Ain3 as R? Is there any specific settings to be done in order to give RGB properly to the chip?

    Thank you.

  • 0
    •  Analog Employees 
    on Sep 20, 2021 7:18 AM in reply to KBK

    Hi,

      "The analog input muxes of the ADV7403 must be controlled directly. This is referred to as manual input muxing.     The manual muxing is activated by setting the ADC_SWITCH_MAN bit. It only affects the analog switches in front of the ADCs.

    Please note PRIM_MODE and VID_STD still have to be set so that the follow on blocks process the video data in the correct format." 

    Refer below configuration for 0xC3 & 0xC4 for processing the RGB inputs using AIN pins.

      Ain1 as G    ADC0_SW[3:0]  0xc3   -  0001
      Ain2 as B    ADC2_SW [3:0] 0xC4   -  0010
      Ain3 as R    ADC1_SW [3:0] 0xc3  -    0011

    Note:  The manual muxing is activated by setting the ADC_SW_MAN_EN bits. It only affects the analogue switches in front of the ADCs. PRIM_MODE and VID_STD still have to be set so the follow-on blocks process the video data in the correct format. Which means: If the settings of INSEL and the manual input muxing registers (ADC0/1/2/3_SW) contradict each other, the ADC0/1/2/3_sw settings apply and INSEL is ignored. For more details please refer Page 19 in ADV7403 manual.

    Thanks,

    Poornima

  • Hi,

    Thank you for your reply.

    I am able to detect the output from ADV7403, confirmed the detection using Status register 0x12[6].

    But I have some questions regarding the output.

    In my case, the PRIM_MODE will be set to SD? Can you please let me know the values for PRIM_MODE and VID_STD in my case.

    If I need the output in BT.656 format, should I set any other register values?
     
    I wanted to confirm whether the output whatever I am able to capture with the given script is in BT.656 format.

    Can I use any other status registers to confirm the output data format? 

    Thank you.

  • 0
    •  Analog Employees 
    on Sep 21, 2021 1:10 PM in reply to KBK

    Hi,

       Generally PRIM_MODE and VID_STD are used to set up the free run modes.These controls are used to specify the free run output standard. Please refer table 12 in ADV7403 manual for setting the PRIM_MODE and VID_STD based upon your formats.

     Regarding BT.656 output, Please configure the OF_SEL[3:0] register for BT.656 setting & refer below snap for your reference,
         

    Thanks,

    Poornima