Hello
We have a request regarding HDMI product ADV7513.
The engineer is evaluating this chip on their own PCB.
He is going to use it as an HDMI converter however he cannot achieve the required result.
Their mode:
Input: 1080p25 4:2:2 YCrCb 8bit embeded sync
Output: They need 1080p60.
Is it possible to implement?
They just have at the output 1080p25. May be they have some errors in the coding? Please find it attached
{
auto temp = readReg( 0x41 );
// temp |= 1<<1;// генерация SYNC adjust enable
temp &= ~(1<<6);
writeReg( 0x41, temp );
}
writeReg( 0x48, 0x00);
writeReg( 0x49, 0xa8);
writeReg( 0x4c, 0x00);
//
// // fixed registers that must be set on power up
writeReg( 0x96, 0xa4);
writeReg( 0x98, 0x03);
writeReg( 0x99, 0x02);
writeReg( 0x9a, 0xe0 );
writeReg( 0x9C, 0x30 );
writeReg( 0x9d, 0x61 );//0x61
writeReg( 0xA2, 0xA4 );
writeReg( 0xA3, 0xA4 );
writeReg( 0xA5, 0x04 );
writeReg( 0xAB, 0x40 );
writeReg( 0xba, 0x60 );
writeReg( 0xbb, 0x00 );
writeReg( 0xd1, 0xff );
writeReg( 0xdc, 0x00 );
writeReg( 0xdd, 0x00 );
writeReg( 0xde, 0xd8 );//0xd8
writeReg( 0xdf, 0x01 );
writeReg( 0xe0, 0xd0 );
writeReg( 0xE4, 0x60 );
writeReg( 0xf9, 0x00 );
writeReg( 0xfa, 0x00 );
writeReg( 0xfd, 0xe0 );
writeReg( 0xfe, 0x80 );
{
auto temp = readReg( 0xe2 );
temp |= 1<<1; //CEC enable ??
writeReg( 0xe2, temp );
}
{
auto temp = readReg( 0xd0 );
temp &= ~(1<<1); //генерация синхросигнала DE
temp |= 1<<1; //генерация синхросигнала DE
temp |= 3<<2; //
temp &= ~(0xf<<4);
temp |= 0x0f<<4; //invert clock
writeReg( 0xd0, temp );
}
{
auto temp = readReg( 0xd6 );
temp |= 1<<4; //TMDS CLK Soft Turn On
// temp |= 1<<0; //gated clock
writeReg( 0xd6, temp );
}
{
auto temp = readReg( 0x15 );
temp &= ~0xF;
temp |= 0x04;
writeReg( 0x15, temp );
}
// ставим 8 бит
{
auto temp = readReg( 0x16 );
temp &= ~(3<<2);//style 2
temp |= 1<<2;//style 2
temp &= ~(3<<4);
temp |= 3<<4;//Color Depth for Input Video Data 8 bit
temp &= ~(1<<0);//0 = RGB 1 = YCbCr
temp |= 1<<0;//0 = RGB 1 = YCbCr
writeReg( 0x16, temp );
}
/**********************************************/
/*********embeded sync*************************/
{
auto temp = readReg( 0xfb );
temp &= ~(3<<1);
temp |= 1<<2; //Low Refresh Rate 25Hz
writeReg( 0xfb, temp );
}
writeReg( 0x30, 0x84);
writeReg( 0x31, 0x02);
writeReg( 0x32, 0xc0);
writeReg( 0x33, 0x10);//1080p-50/60
writeReg( 0x34, 0x05 );
writeReg( 0x35, 0x2f );
writeReg( 0x36, 0xe9 );
writeReg( 0x37, 0x0f );
writeReg( 0x38, 0x00 );
writeReg( 0x39, 0x43 );
writeReg( 0x3a, 0x80 );
writeReg( 0xd7, 0x84 );
writeReg( 0xd8, 0x02 );
writeReg( 0xd9, 0xc0 );
writeReg( 0xda, 0x10);//1080p-50/60
writeReg( 0xdb, 0x05 );//
/**********************************************/
{
auto temp = readReg( 0x17 );
temp &= ~(3<<5);// sync polarity
// temp |= 1<<6;// sync polarity
temp &= ~(1<<2);
temp |= 1<<0; // DE embeded sync
temp |= 1<<1; //aspect ratio 16:9
writeReg( 0x17, temp); //temp BVA!!
}
{
auto temp = readReg( 0x16 );
temp &= ~(1<<7);//4:4:4 output|
writeReg( 0x16, temp );
}
writeReg( 0x40, 0x80 );
{
auto temp = readReg(0x18);
temp |= 1<<7;//csc enable
temp &= ~(3<<5);
//temp |= 1<<5;
writeReg( 0x18, temp );
}
{
auto temp = readReg( 0xAF );
temp &= ~(1<<1);//DVI b0 HDMI b1
temp |= 1<<1;//DVI b0 HDMI b1
writeReg( 0xAF, temp );
}
/**********CSC coefficients********************/
writeReg( 0x18, 0xe7 );
writeReg( 0x19, 0x34 );
writeReg( 0x1a, 0x04 );
writeReg( 0x1b, 0xad );
writeReg( 0x1c, 0x00 );
writeReg( 0x1d, 0x00 );
writeReg( 0x1e, 0x1c );
writeReg( 0x1f, 0x1b );
writeReg( 0x20, 0x1d );
writeReg( 0x21, 0xdc );
writeReg( 0x22, 0x04 );
writeReg( 0x23, 0xad );
writeReg( 0x24, 0x1f );
writeReg( 0x25, 0x24 );
writeReg( 0x26, 0x01 );
writeReg( 0x27, 0x35 );
writeReg( 0x28, 0x00 );
writeReg( 0x29, 0x00 );
writeReg( 0x2a, 0x04 );
writeReg( 0x2b, 0xad );
writeReg( 0x2c, 0x08 );
writeReg( 0x2d, 0x7c );
writeReg( 0x2e, 0x1b );
writeReg( 0x2f, 0x77 );
/************************************/
// Audio init
writeReg( 0x01, 0x00 );
writeReg( 0x02, 0x18 );
writeReg( 0x03, 0x00 );
{
auto temp = readReg( 0x0a );
temp &= ~(7<<4);
writeReg( 0x0a, temp );
}
{
auto temp = readReg( 0x0b );
temp &= ~(1<<7);//SPDIF disable
writeReg( 0x0b, temp );
}
{
auto temp = readReg( 0x0c );
temp &= ~(0x0f<<2);
temp |= 0x0f<<2;//enable I2S
writeReg( 0x0c, temp );
}
{
auto temp = readReg( 0x15 );
temp &= ~(0x0f<<4);
temp |= 1<<5;
writeReg( 0x015, temp );
}
{
auto temp = readReg( 0x0a );
temp &= ~(3<<2);
temp |= 3<<2;
writeReg( 0x0a, temp );
}
/************HDCP INIT**************/
// {
// auto temp = readReg( 0xAF );
// temp |= 1<<4;
// temp |= 1<<7;
// writeReg( 0xAF, temp );
// }
///***** ожидание старта HDCP******/
// { auto temp = readReg( 0x97 );
// temp &= 0x40;
// while (temp==0)
// {
// temp = readReg( 0x97 );
// temp &= 0x40;
// }
// temp |= 1<<6;
// writeReg( 0x97, temp );
// }
// {
// auto temp = readReg( 0xc8 );
// temp &= 0x04;
// while (temp==0)
// {
// temp = readReg( 0xc8 );
// temp &= 0x04;
// }
// }
//
/***********************************/
/********** AVIInfoFrame***********/
{
auto temp = readReg( 0x4a );
temp &= ~(7<<5);
temp |= 3<<5; //1 = Use automatically generated checksum 1 = AVI Packet I2C update active 1 = Audio InfoFrame Packet I2C update active
writeReg( 0x4a, temp );
}
{
auto temp = readReg( 0x52 );
temp &= ~(7<<0);
temp |= 0x02<<0; //version of InfoFrame
writeReg( 0x52, temp );
}
{
auto temp = readReg( 0x53 );
temp &= ~(0x0f<<0);
temp |= 0x0d<<0; //length of InfoFrame
writeReg( 0x53, temp );
}
/*****Like in AD source**********/
{
auto temp = readReg( 0x3b );//pixel repeat mode 0x3B[6:5] to 0b10 or 0b11.
temp &= ~(3<<5); // auto mode
//temp |= 1<<6; // manual mode
// temp |= 1<<5; // max mode
writeReg( 0x3b, temp );
}
{
auto temp = readReg( 0x3b );//pixel repeat mode 0x3B[6:5] to 0b10 or 0b11.
temp &= ~(3<<1); // pixel repetition
temp |= 1<<1; // pixel repetition
writeReg( 0x3b, temp );
}
{
auto temp = readReg( 0x3b );//pixel repeat mode 0x3B[6:5] to 0b10 or 0b11.
// temp &= ~(3<<3); // input freq mult
// temp |= 1<<3; // input freq mult
writeReg( 0x3b, temp );
}
{
auto temp = readReg(0x3c);//
temp &= ~(0x3f<<0); //
temp |= 0x10<<0; // //1080p-60
// temp |= 0x1f<<0; // //1080p-50
// temp |= 0x22<<0; // //1080p-30
// temp |= 0x4<<0; // //1080p-25
writeReg(0x3d,temp);
}
{
auto temp = readReg( 0x55 );
temp &= ~(3<<5);//RGB
temp |= 1<<6; //YCrCb 4:4:4
writeReg( 0x55, temp );
}
{
auto temp = readReg( 0x56 );
temp &= ~(3<<4);//aspect ratio
temp |= 1<<5; //aspect ratio 16:9
temp &= ~(0x0f<<0);//
temp |= 1<<3;////aspect ratio 16:9
writeReg( 0x56, temp );
}
time_service::delay_ms(20);
Regards
Evgeny
