ADV7480 I2C Salve Address - ADV7481_UG-747.pdf

Hi 

We found something wrong at page 85 in ADV7481_UG-747.pdf 

DPLL_SALVE_ADDR [6:0] should be DPLL_SLAVE_ADDR [7:1]

REPEATER_SLAVE_ADDR [6:0] should be REPEATER_SALVE_ADDR [7:1]

CBUS_SALVE_ADDR [6:0] should be CBUS_SALVE_ADDR [7:1] 

Could you help to clarify them?  

which one is correct ?   [6:0]  or [7:1] ?

 I2C salve is 7-Bit addresses for ADV7480? or 8 Bit addresses ?

Thanks. 



SALVE addresses : 7Bit or 8Bit?
[edited by: gen at 4:09 PM (GMT -4) on 23 Jul 2021]
  • 0
    •  Analog Employees 
    on Jul 26, 2021 8:29 AM

    Hi,

      I2C salve is 7-Bit addresses for ADV7480? or 8 Bit addresses ? 

         We use 8bit I2C addressing not 7bit and our i2c driver work with 8-bit address (i.e It's a combination of the 7-bit address plus the R/W bit), So there might be typo error in the "ADV7481_UG-747.pdf".

    Note: ADV748x maps acts as a standard slave device on the bus. The data on the SDA pin is eight bits long, supporting the 7-bit addresses plus the R/W bit.

    Thanks,

    Poornima

  • Hi 

    Please help to clarify 

    How many is minimal horizontal blanking of ADV7480?

    How many is minimal vertical blanking of ADV7480? 

    What value is VC and DT in MIPI output package of ADV7480?

    How to setup value of VC and DT ?  

    Thanks. 

  • 0
    •  Analog Employees 
    on Aug 2, 2021 5:20 PM in reply to gen

    Hi,

      Generally all video parts ADV7480) will send the video data(active region) + blanking data(non-active region) and note that in the blanking areas, HDMI will carry the audio and infoframe packages.

      For example NTSC format like 525 lines will include 480 active lines and 45 blanking lines (480+45).

     Horizontal and vertical blanking period are different for different formats, so minimum and maximum blanking will vary depending upon the formats.  For more details Please refer HDMI1.4 specification document.

    Please note MIPI signals on ADV7480  have been set to be compliant to the D-PHY specification and these are specified in the datasheet "MIPI Video output specifications" section.

     These details we can check with MIPI DPHY version 1.00.00 specification to check whether the output data format is compliance with MIPI-CSI2 Specifications.

     The Virtual Channel identifier is controlled by CSI map, register 0x0D bits 7:6.  By default these register bits are 0b'00. Therefore by default and in all ADI scripts the Virtual Channel identifier is set to 0b'00".

    We need to set the virtual channel identifier bits used in Data Identifier bytes. Data identifier bytes are used in MIPI CSI-2 data packets.

    Please note that for our MIPI evaluation we used the MIPI reference termination board available from here:
      https://www.iol.unh.edu/solutions/test-tools/mipi

     Also you would need to have good termination in your MIPI receiver.These details are provided by expert in AN-1337 - https://www.analog.com/media/en/technical-documentation/application-notes/AN-1337.pdf

    Thanks,

    Poornima

  • Hi , 
    Which registers in ADV7480 can define 

    1. Minimal horizontal blanking with MIPI-CSI2 output

    2. Minimal vertical blanking with MIPI-CSI2 output

    or these values are defined in HDMI infoframe (all of video parts)?

     

    Thanks. 

  • 0
    •  Analog Employees 
    on Aug 3, 2021 12:16 PM in reply to gen

    Hi,

     There are some registers available in user guide to find out the blanking, total line width & active video. Please refer Page 88/92 in Userguide UG-747 (Rev. 0) (analog.com)

     For example:
         Line_width -  Active video
         Total_line_width - Active video+blanking


    Thanks,

    Poornima