ADV7181C :- RGB 444 DDR output format

Hello,

The requirement is as follows :-
Input :- PAL interlaced video
Resolution :- 720 * 576 @25i
Output from the decoder :- RGB 444 DDR video data format
Timing signals to the FPGA :- vsync, hsync and data valid

In order to obtain the above requirement the following register set was modified
{0x42,0xC9,0x0C},//DDR enable
 {0x42,0x6B,0x84},//RGB 444 and Data valid signal
 {0x42,0x7B,0x1D},//Turn off EAV and SAV Codes

It would be helpful if you verify this register sets, Can I know what other register sets need to be changed for the above requirement ?

To convert to RGB, CSC have to be enabled, what are the preferred values for CSC registers ?

When tried to change the vsync and hsync polarity by modifying the 0x85 register, there was no changes observed in the CRO.

Thanks,

Arpitha

  • 0
    •  Analog Employees 
    on Jul 23, 2021 5:39 PM

    Hi,

      In 0x85 register, Have you enabled the POL_MAN_EN bit to use POL_VS and POL_HS ?

      Please let us know, why color space conversation is required from your end?

    Thanks,

    Poornima

  • Hello,

    In 0x85 register, I have enabled and checked the POL_MAN_EN bit as well to use POL_VS and POL_HS, but still I see the same observation

    The input to decoder is PAL interlaced which will be of color format YCbCr, but the output from the decoder has to be RGB444, so we need CSC, am I correct?

    Thanks,

    Arpitha

  • Hello,

    The CVBS input is connected to the Ain1 of the decoder chip

    When tried with different decoder configuration and when the status register was read,
    following are the observation

    1)Since the output from the decoder is expected to be RGB444 DDR mode,we have to enable the CP processor,
    so according to it we configure the 0x05 register in CP mode and 0x06  register  to 720*576, 
    {0x42,0x05,0x01},
    {0x42,0x06,0x01}/{0x42,0x06,0x0B}
    but in this case we are not able to observe any output
    even when the register 0xBF was set to get the forced output, there is no output seen
    The status register 0x12 when read gives value as 0x40.
    The status register 0x13 when read gives value as 0xD.

    2)When the register is configured to SDP mode i.e.
    {0x42,0x05,0x00},
    {0x42,0x06,0x02},

    The output observed is overlapping of two colours.

    Here, The status register 0x12 when read gives value as 0xC0.
    The status register 0x13 when read gives value as 0xED.

    Is it like the component processor wont receive the CVBS connected to Ain1 input of decoder?

    I have attached the decoder configuration, It would be helpful, if you verify it.

    PAL_ADV7181C_REG_dec1 pal_iic_dec1[NUMBER_OF_ADV7181C_REGS_dec1] =
     {
    		 {0x42,0x00,0x00},
    		 {0x42,0x01,0xC8},
    		 {0x42,0x02,0x04},
    		 {0x42,0x03,0x0C},
    		 {0x42,0x04,0x7F},//[3] :-HS,VS,F forced active
         	 {0x42,0x05,0x01},//component video
             {0x42,0x06,0x0B},//625i 4X1 (720x576)//101
    		 {0x42,0x07,0x7F},//autodetection enabled
    		 {0x42,0x08,0x80},//Gain 1 for contrast
    		 {0x42,0x0A,0x00},//00h = 0IRE brightness
    		 {0x42,0x0B,0x00},//HUE range
    		 {0x42,0x0C,0x36},//default y value and free run mode for blue screen
    		 {0x42,0x0D,0x7C},//Default Value C
    		 {0x42,0x0E,0x00},//0x0E ADI Control
    		 {0x42,0x0F,0x00},// Power Management and chip rst
    		 {0x42,0x10,0x4D}, //status reg read only
    		 {0x42,0x11,0x19},//info reg read only
    		 {0x42,0x12,0xC0}, //status 2 read only
    		 {0x42,0x13,0xED},//status 3 read only for SD detected and interlaced detection
    		 {0x42,0x13,0x00},//
    		 {0x42,0x14,0x12},
    		 {0x42,0x15,0x00},//digital clamp
    		 {0x42,0x16,0x00},
    		 {0x42,0x17,0x41},//filter
    		 {0x42,0x18,0x93},//filter
    		 {0x42,0x19,0xF1},// Comb Filter Control
    		 {0x42,0x1A,0x10},//reserved
    		 {0x42,0x1B,0x58},////reserved
    		 {0x42,0x1C,0x10},//reserved
    		 {0x42,0x1D,0x47},//Use 28MHz Crystal
    		 {0x42,0x1E,0x00},
    		 {0x42,0x1F,0x00},
    		 {0x42,0x20,0x77},
    		 {0x42,0x21,0xF1},
    		 {0x42,0x22,0x13},
    		 {0x42,0x23,0xCC},
    		 {0x42,0x24,0xBF},
    		 {0x42,0x25,0xD8},
    		 {0x42,0x26,0xF4},
    		 {0x42,0x27,0x58},// Pixel Delay Control
    		 {0x42,0x28,0x10},//reserved
    		 {0x42,0x29,0xC0},//reserved
    		 {0x42,0x2A,0xFC},//reserved
    		 {0x42,0x2B,0xE1},//Misc Gain Control
    		 {0x42,0x2C,0xAE},//AGC Mode Control
    		 {0x42,0x2D,0xFF},//Chroma Gain Control 1 Write Only
    		 {0x42,0x2D,0xF4},//Chroma Gain Control 1 Write Only
    		 {0x42,0x2E,0xFF},//Chroma Gain Control 2
    		 {0x42,0x2E,0x00},//Chroma Gain Control 2
    		 {0x42,0x2F,0xFE},//Luma gain 1
    		 {0x42,0x2F,0xFF},
    		 {0x42,0x30,0xD9},//Luma gain 2
    		 {0x42,0x30,0xFF},
    		 {0x42,0x31,0x02},//000 1/0 1/0 010
    		 {0x42,0x31,0x22},//[5] :- 1/0 Manual VS/field / EAV-SAV
    		 {0x42,0x32,0x41},//[6]:- 1 (VS changes state at start of line for even field) [7]:- 1 (VS at odd field)
    		 {0x42,0x33,0x84},//vsync field control [7]:- 1 (VS changes state at start of line for odd field)
    		 {0x42,0x34,0x00},//HSE and HSB
    		 {0x42,0x35,0x02},//HSB[7:0]
    		 {0x42,0x36,0x00},//HSE[7:0]
    		 {0x42,0x37,0x01},//timing polarity
    		 {0x42,0x38,0x80},// NTSC comb control
    		 {0x42,0x39,0xC0},//PAL comb control
    		 {0x42,0x3A,0x17},//[7:4] :- LLC range ; ADC0 to ADC3 operation
    		 {0x42,0x3B,0x81},//BiAS control
    		 {0x42,0x3C,0x58},//50uA ;
    		 {0x42,0x3D,0xA2},//Manual Window
    		 {0x42,0x3E,0x6A},//reserved
    		 {0x42,0x3F,0xA0},//reserved
    		 {0x42,0x40,0x90},//reserved
    		 {0x42,0x41,0x01},//resampling control
    		 {0x42,0x42,0x7E},
    		 {0x42,0x43,0xA4},
    		 {0x42,0x44,0xFF},
    		 {0x42,0x45,0xB6},
    		 {0x42,0x46,0x12},
    		 {0x42,0x48,0x00},//Gemstar Control 1
    		 {0x42,0x49,0x00},
    		 {0x42,0x4A,0x00},
    		 {0x42,0x4B,0x00},
    		 {0x42,0x4C,0xF0},
    		 {0x42,0x4D,0xEF},//CTI DNR )digital Noise reduction)
    		 {0x42,0x4E,0x08},
    		 {0x42,0x4F,0x08},//reserved
    		 {0x42,0x50,0x08},
    		 {0x42,0x51,0x24},		//lock count//only in SDP mode
    		 {0x42,0x52,0x04},
    		 {0x42,0x53,0x00},
    		 {0x42,0x54,0x78},
    		 {0x42,0x55,0x23},
    		 {0x42,0x56,0x8C},
    		 {0x42,0x57,0xC5},
    		 {0x42,0x58,0xBB},
    		 {0x42,0x59,0x00},
    		 {0x42,0x5A,0x00},
    		 {0x42,0x5B,0x28},
    		 {0x42,0x5C,0x94},
    		 {0x42,0x5D,0x00},
    		 {0x42,0x5E,0x05},
    		 {0x42,0x5F,0xDB},
    		 {0x42,0x60,0x00},
    		 {0x42,0x61,0x00},
    		 {0x42,0x62,0x00},
    		 {0x42,0x63,0x01},
    		 {0x42,0x64,0x05},
    		 {0x42,0x65,0x25},
    		 {0x42,0x66,0xDB},
    		 {0x42,0x67,0x00},
    		 {0x42,0x68,0x01},//CSC23 selectn based on ip
    		 {0x42,0x69,0x04},//configure (0x00)
    		 {0x42,0x6A,0x40}, //[5]:-1 Bypass DLL block
    		 {0x42,0x6B,0x84},//Enable DE output
    		 {0x42,0x6C,0x00},// CP Clamp1
    		 {0x42,0x6D,0x00},// CP Clamp1
    		 {0x42,0x6E,0x00},// CP Clamp1
    		 {0x42,0x6F,0x00},// CP Clamp1
    		 {0x42,0x70,0x00},// CP Clamp1
    		 {0x42,0x71,0x00},// CP AGC 1
    		 {0x42,0x72,0x99},// CP AGC 2
    		 {0x42,0x73,0xF0},// CP AGC 1
    		 {0x42,0x74,0x0C},// CP AGC 1
    		 {0x42,0x75,0x03},// CP AGC 1
    		 {0x42,0x76,0x00},// CP AGC 1
    		 {0x42,0x77,0x04},// CP OFFSET1
    		 {0x42,0x78,0x01},// CP OFFSET1
    		 {0x42,0x79,0x00},// CP OFFSET1
    		 {0x42,0x7A,0x40},// CP OFFSET1
    		 {0x42,0x7B,0x1D},//CP AV CONTROL [1]:- 0 (dont insert AV codes)
    		 {0x42,0x7C,0xC0},//polarity [5]:-0 :-FIELD/DE active high
    		 {0x42,0x7D,0x00},//END HS
    		 {0x42,0x7E,0x00},//start HS
    		 {0x42,0x7F,0x00},//END VS
    		 {0x42,0x80,0x00},//start VS
    		 {0x42,0x81,0xF0},//default
    		 {0x42,0x82,0x04},//default
    		 {0x42,0x83,0x00},//CP measure control 3
    		 {0x42,0x84,0x0C},//No Filtering
    		 {0x42,0x85,0xE2},
    		 {0x42,0x86,0x0B},//Cp misc control
    		 {0x42,0x87,0x63},//CP TLLC CONTROL 1 [7]:- 0 (PLL auto detect through PRIM mode and Vid Std)
    		 {0x42,0x88,0x5A},//CP TLLC CONTROL 2 default
    		 {0x42,0x89,0x08},//CP TLLC CONTROL 3 SDP op formatting
    		 {0x42,0x8A,0x10},//CP TLLC CONTROL 4 [7]:-Automatic VCO Range selection and default
    		 {0x42,0x8B,0x02},//RO
    		 {0x42,0x8C,0x49},//RO
    		 {0x42,0x8D,0x03},//RO
    		 {0x42,0x8E,0x5B},//RO
    		 {0x42,0x8F,0x00},//RO
    		 {0x42,0x8F,0x00},//RO
    		 {0x42,0x90,0x00},//RO
    		 {0x42,0x90,0x00},/RO
    		 {0x42,0x91,0x50},
    		 {0x42,0x92,0xFF},//RO
    		 {0x42,0x92,0x00},//RO
    		 {0x42,0x93,0xFF},//RO
    		 {0x42,0x93,0x00},//RO
    		 {0x42,0x94,0xFF},//RO
    		 {0x42,0x94,0x00},//RO
    		 {0x42,0x95,0xFF},//RO
    		 {0x42,0x95,0x00},//RO
    		 {0x42,0x96,0xE0},//RO
    		 {0x42,0x96,0x00},//RO
    		 {0x42,0x97,0xFF},//RO
    		 {0x42,0x97,0x00},//RO
    		 {0x42,0x98,0xFF},//RO
    		 {0x42,0x98,0x00},//RO
    		 {0x42,0x99,0xFF},//RO
    		 {0x42,0x99,0x00},//RO
    		 {0x42,0x9A,0xFF},//RO
    		 {0x42,0x9A,0x00},//RO
    		 {0x42,0x9B,0xFF},//RO
    		 {0x42,0x9B,0x00},//RO
    		 {0x42,0x9C,0xFF},// R or write
    		 {0x42,0x9C,0x08},
    		 {0x42,0x9D,0xFF},//RO
    		 {0x42,0x9D,0x08},
    		 {0x42,0x9E,0xF7},
    		 {0x42,0x9F,0xF9},
    		 {0x42,0xA0,0xFF},//RO
    		 {0x42,0xA0,0x03},//RO
    		 {0x42,0xA1,0xFF},//RO
    		 {0x42,0xA1,0xFF},//RO
    		 {0x42,0xA2,0xFF},//reserved
    		 {0x42,0xA2,0x00},
    		 {0x42,0xA3,0xFF},//RO
    		 {0x42,0xA3,0x00},//RO
    		 {0x42,0xA4,0xFF},//RO
    		 {0x42,0xA4,0xFF},//RO
    		 {0x42,0xA5,0xFF},//RO
    		 {0x42,0xA5,0x04},//RO
    		 {0x42,0xA6,0xFF},//reserved
    		 {0x42,0xA6,0x1E},//reserved
    		 {0x42,0xA7,0xFF},//RO
    		 {0x42,0xA7,0x00},//RO
    		 {0x42,0xA8,0xFF},//RO
    		 {0x42,0xA8,0x00},//RO
    		 {0x42,0xA9,0xFF},//RO
    		 {0x42,0xA9,0x00},//RO
    		 {0x42,0xAA,0xFF},//RO
    		 {0x42,0xAA,0x00},//RO
    		 {0x42,0xAB,0xFF},//RO
    		 {0x42,0xAB,0x00},//RO
    		 {0x42,0xAC,0xFF},//RO
    		 {0x42,0xAC,0x00},//RO
    		 {0x42,0xAD,0xFF},//RO
    		 {0x42,0xAD,0x00},//RO
    		 {0x42,0xAE,0x60},//RO
    		 {0x42,0xAE,0x03},//RO
    		 {0x42,0xAF,0xC0},//RO
    		 {0x42,0xAF,0x00},//RO
    		 {0x42,0xB0,0x00},//RO
    		 {0x42,0xB0,0x00},//RO
    		 {0x42,0xB1,0x6F},//RO
    		 {0x42,0xB1,0x3F},//RO
    		 {0x42,0xB2,0x1C},////RO
    		 {0x42,0xB2,0xFF},//RO
    		 {0x42,0xB3,0x54},//WO CP Free
    		 {0x42,0xB3,0x00},//RO
    		 {0x42,0xB4,0x00},//RO
    		 {0x42,0xB4,0x00},//RO
    		 {0x42,0xB5,0x00},//RB std
    		 {0x42,0xB5,0x83},
    		 {0x42,0xB6,0x00},
    		 {0x42,0xB6,0x00},
    		 {0x42,0xB7,0x13},
    		 {0x42,0xB7,0x00},
    		 {0x42,0xB8,0x03},
    		 {0x42,0xB8,0x40},
    		 {0x42,0xB9,0x33},
    		 {0x42,0xB9,0x00},
    		 {0x42,0xBA,0x40},
    		 {0x42,0xBB,0x09},
    		 {0x42,0xBC,0x2F},
    		 {0x42,0xBD,0xFF},
    		 {0x42,0xBE,0xE0},
             {0x42,0xBF,0x02},///CP DEF COL 1 [2]:- 1 output default colour
    		 {0x42,0xC0,0x32},//CP DEF COL 2
    		 {0x42,0xC1,0x30},//CP DEF COL 3
    		 {0x42,0xC2,0x30},//CP DEF COL 4
    		 {0x42,0xC3,0x46},//ADC switch 1 Ain 4 and Ain 6
    		 {0x42,0xC4,0x35},//
    		 {0x42,0xC5,0x91},// Clamp Averaging
    		 {0x42,0xC6,0x00},//reserved
    		 {0x42,0xC7,0x00},//reserved
    		 {0x42,0xC8,0x00},//reserved
    		 {0x42,0xC9,0x08},//DDR13.5 and [2]:- 1 for red component out firs
    		 {0x42,0xCA,0x08},//RO field length count
    		 {0x42,0xCB,0x08},//RO field length count
    		 {0x42,0xCC,0x5B},//Reserved
    		 {0x42,0xCD,0x00},//Reserved
    		 {0x42,0xCE,0x01},
    		 {0x42,0xCF,0xB4},
    		 {0x42,0xD0,0x00},
    		 {0x42,0xD1,0x10},
    		 {0x42,0xD2,0xFF},
    		 {0x42,0xD3,0xFF},
    		 {0x42,0xD4,0x7F},
    		 {0x42,0xD5,0x7F},
    		 {0x42,0xD6,0x3E},
    		 {0x42,0xD7,0x08},
    		 {0x42,0xD8,0x3C},
    		 {0x42,0xD9,0x08},
    		 {0x42,0xDA,0x3C},
    		 {0x42,0xDB,0x9B},
    		 {0x42,0xDC,0xAC},// Letterbox Contorl 1
    		 {0x42,0xDD,0x4C},// Letterbox Contorl 2
    		 {0x42,0xDE,0x08},//RO
    		 {0x42,0xDE,0x00},//RO
    		 {0x42,0xDF,0x0C},//RO
    		 {0x42,0xDF,0x00},//RO
    		 {0x42,0xE0,0x14},//reserved
    		 {0x42,0xE1,0x80},// SD Offset Cb
    		 {0x42,0xE2,0x80},// SD Offset Cr
    		 {0x42,0xE3,0x80},//SD Saturation Cb
    		 {0x42,0xE4,0x80},// SD Saturation Cr
    		 {0x42,0xE5,0x25},//NTSC V bit begin [4:0]:- NTSC default
    		 {0x42,0xE6,0x04},//NTSC
    		 {0x42,0xE7,0x63},//NTSC
    		 {0x42,0xE8,0x65},//PAL V bit begin
    		 {0x42,0xE9,0x14},//PAL V bit end
    		 {0x42,0xEA,0x63},// PAL F bit toggle
    		 {0x42,0xEB,0x55},//V blank control 1
    		 {0x42,0xEC,0x55},//V blank control 2
    		 {0x42,0xED,0x00},//FB control
    		 {0x42,0xED,0x12},//FB status read only
    		 {0x42,0xEE,0x00},//FB control
    		 {0x42,0xEF,0x4A},//FB control
    		 {0x42,0xF0,0x44},//FB control
    		 {0x42,0xF1,0x0C},//FB control
    		 {0x42,0xF2,0x32},
    		 {0x42,0xF3,0x01},//AFE_CONTROL 1
    		 {0x42,0xF4,0x37},
    		 {0x42,0xF5,0xE0},//reserved
    		 {0x42,0xF6,0x69},//reserved
    		 {0x42,0xF7,0x10},//reserved
    		 {0x42,0xF8,0x00},//IF filter
    		 {0x42,0xF9,0x03},// VS Mode Control
    		 {0x42,0xFA,0xA0},//reserved
    		 {0x42,0xFB,0x40},//peaking control
    		 {0x42,0xFC,0x04},//Coring Threshold 2 //DNR
     };
    

    Thanks,

    Arpitha

  • 0
    •  Analog Employees 
    on Jul 26, 2021 2:31 PM in reply to ArpithaShetty

    Hi,

     Could you please compare your configuration with "##CP YPrPb 525i & 625i##
    :625I YPrPb In 12Bit RGB DDR HS/VS HDMI:" at 5355.ADV7181C_Evaluation_Software.zip

    Thanks,

    Poornima

  • Hello,

    I have compared the configuration.

    With that configuration as well I wont get the output

    The doubt what I have here is, whether the component processor in the decoder will receive the CVBS input given Ain1 input of decoder

    Thanks,

    Arpitha